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MC74ACT373MELG PDF预览

MC74ACT373MELG

更新时间: 2024-11-14 05:22:19
品牌 Logo 应用领域
安森美 - ONSEMI 锁存器
页数 文件大小 规格书
12页 117K
描述
Octal Transparent Latch with 3−State Outputs

MC74ACT373MELG 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:SOIC包装说明:SOP, SOP20,.3
针数:20Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.08
系列:ACTJESD-30 代码:R-PDSO-G20
JESD-609代码:e4长度:12.575 mm
负载电容(CL):50 pF逻辑集成电路类型:BUS DRIVER
最大I(ol):0.024 A位数:8
功能数量:1端口数量:2
端子数量:20最高工作温度:85 °C
最低工作温度:-40 °C输出特性:3-STATE
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP20,.3
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
包装方法:TAPE AND REEL峰值回流温度(摄氏度):260
电源:5 VProp。Delay @ Nom-Sup:11.5 ns
传播延迟(tpd):11.5 ns认证状态:Not Qualified
座面最大高度:2.05 mm子类别:FF/Latches
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:40宽度:5.275 mm
Base Number Matches:1

MC74ACT373MELG 数据手册

 浏览型号MC74ACT373MELG的Datasheet PDF文件第2页浏览型号MC74ACT373MELG的Datasheet PDF文件第3页浏览型号MC74ACT373MELG的Datasheet PDF文件第4页浏览型号MC74ACT373MELG的Datasheet PDF文件第5页浏览型号MC74ACT373MELG的Datasheet PDF文件第6页浏览型号MC74ACT373MELG的Datasheet PDF文件第7页 
MC74AC373, MC74ACT373  
Octal Transparent Latch  
with 3−State Outputs  
The MC74AC373/74ACT373 consists of eight latches with 3−state  
outputs for bus organized system applications. The flip−flops appear  
transparent to the data when Latch Enable (LE) is HIGH. When LE is  
LOW, the data that meets the setup time is latched. Data appears on the  
bus when the Output Enable (OE) is LOW. When OE is HIGH, the bus  
output is in the high impedance state.  
http://onsemi.com  
Features  
PDIP−20  
Eight Latches in a Single Package  
3−State Outputs for Bus Interfacing  
Outputs Source/Sink 24 mA  
N SUFFIX  
CASE 738  
1
ACT373 Has TTL Compatible Inputs  
Pb−Free Packages are Available  
SOIC−20W  
DW SUFFIX  
CASE 751D  
V
O
D
D
O
O
D
D
O
4
LE  
11  
CC  
7
7
6
6
5
5
4
1
20  
19  
18  
17  
16  
15  
14  
12  
13  
TSSOP−20  
DT SUFFIX  
CASE 948E  
1
1
2
3
4
5
6
7
9
8
10  
OE  
O
D
D
O
O
D
D
O
3
GND  
0
0
1
1
2
2
3
Figure 1. Pinout: 20−Lead Packages Conductors  
SOEIAJ−20  
M SUFFIX  
CASE 967  
(Top View)  
1
PIN ASSIGNMENT  
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
PIN  
FUNCTION  
dimensions section on page 8 of this data sheet.  
D −D  
Data Inputs  
0
7
LE  
Latch Enable Input  
Output Enable Input  
3−State Latch Outputs  
DEVICE MARKING INFORMATION  
See general marking information in the device marking  
section on page 9 of this data sheet.  
OE  
O −O  
0
7
D
D
D
D
D
D
D
D
6 7  
0
1
2
3
4
5
LE  
OE  
O
O O O O O O O  
1 2 3 4 5 6 7  
0
Figure 2. Logic Symbol  
©
Semiconductor Components Industries, LLC, 2006  
1
Publication Order Number:  
November, 2006 − Rev. 8  
MC74AC373/D  

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