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MC741VHC157MEL PDF预览

MC741VHC157MEL

更新时间: 2024-11-11 19:04:27
品牌 Logo 应用领域
安森美 - ONSEMI 光电二极管输出元件逻辑集成电路
页数 文件大小 规格书
11页 173K
描述
IC AHC/VHC SERIES, QUAD 2 LINE TO 1 LINE MULTIPLEXER, TRUE OUTPUT, PDSO16, EIAJ, PLASTIC, SOIC-16, Multiplexer/Demultiplexer

MC741VHC157MEL 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:SOIC
包装说明:SOP,针数:16
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.3系列:AHC/VHC
JESD-30 代码:R-PDSO-G16JESD-609代码:e0
长度:10.2 mm逻辑集成电路类型:MULTIPLEXER
功能数量:4输入次数:2
输出次数:1端子数量:16
最高工作温度:85 °C最低工作温度:-40 °C
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE峰值回流温度(摄氏度):240
传播延迟(tpd):15 ns认证状态:Not Qualified
座面最大高度:2.05 mm最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):2 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:TIN LEAD
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:30
宽度:5.275 mmBase Number Matches:1

MC741VHC157MEL 数据手册

 浏览型号MC741VHC157MEL的Datasheet PDF文件第2页浏览型号MC741VHC157MEL的Datasheet PDF文件第3页浏览型号MC741VHC157MEL的Datasheet PDF文件第4页浏览型号MC741VHC157MEL的Datasheet PDF文件第5页浏览型号MC741VHC157MEL的Datasheet PDF文件第6页浏览型号MC741VHC157MEL的Datasheet PDF文件第7页 
SEMICONDUCTOR TECHNICAL DATA  
The MC74VHC157 is an advanced high speed CMOS quad 2–channel  
multiplexer fabricated with silicon gate CMOS technology. It achieves high  
speed operation similar to equivalent Bipolar Schottky TTL while maintaining  
CMOS low power dissipation.  
It consists of four 2–input digital multiplexers with common select (S) and  
enable (E) inputs. When E is held High, selection of data is inhibited and all  
the outputs go Low.  
The select decoding determines whether the A or B inputs get routed to  
the corresponding Y outputs.  
D SUFFIX  
16–LEAD SOIC PACKAGE  
CASE 751B–05  
The internal circuit is composed of three stages, including a buffer output  
which provides high noise immunity and stable output. The inputs tolerate  
voltages up to 7V, allowing the interface of 5V systems to 3V systems.  
DT SUFFIX  
16–LEAD TSSOP PACKAGE  
CASE 948F–01  
High Speed: t  
= 4.1ns (Typ) at V  
= 5V  
= 4µA (Max) at T = 25°C  
PD  
Low Power Dissipation: I  
CC  
CC  
A
High Noise Immunity: V  
Power Down Protection Provided on Inputs  
Balanced Propagation Delays  
Designed for 2V to 5.5V Operating Range  
= V  
= 28% V  
NIH  
NIL CC  
Low Noise: V  
= 0.8V (Max)  
M SUFFIX  
16–LEAD SOIC EIAJ PACKAGE  
CASE 966–01  
OLP  
Pin and Function Compatible with Other Standard Logic Families  
Latchup Performance Exceeds 300mA  
ESD Performance: HBM > 2000V; Machine Model > 200V  
Chip Complexity: 82 FETs or 20 Equivalent Gates  
ORDERING INFORMATION  
MC74VHCXXXD  
MC74VHCXXXDT  
MC74VHCXXXM  
SOIC  
TSSOP  
SOIC EIAJ  
EXPANDED LOGIC DIAGRAM  
2
A0  
4
3
5
Y0  
B0  
A1  
B1  
PIN ASSIGNMENT  
V
S
1
2
16  
15  
CC  
7
A0  
E
6
Y1  
Y2  
B0  
Y0  
A3  
B3  
Y3  
A2  
B2  
Y2  
3
4
14  
13  
NIBBLE  
INPUTS  
DATA  
OUTPUTS  
11  
10  
14  
13  
A2  
B2  
A3  
B3  
9
A1  
5
6
7
8
12  
11  
10  
9
B1  
Y1  
12  
Y3  
GND  
15  
1
E
S
FUNCTION TABLE  
Inputs  
Outputs  
E
S
Y0 – Y3  
H
L
L
X
L
H
L
A0A3  
B0B3  
A0 – A3, B0 – B3 = the levels of  
the respective Data–Word Inputs.  
6/97  
Motorola, Inc. 1997  
REV 1  
67  

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