Datasheet > 微控制器和处理器 > 微控制器> MC68MH360FE33

MC68MH360FE33

更新时间： 2024-01-02 21:47:53

品牌	Logo	应用领域
摩托罗拉 - MOTOROLA		微控制器和处理器通信控制器外围集成电路时钟
页数	文件大小	规格书
962页	2727K
描述
QUad Integrated Communications Controller Users Manual

阅读下载

中文翻译

获取价格

技术参数
数据手册

如果您发现信息不准确，欢迎纠错

MC68MH360FE33 技术参数

生命周期：	Obsolete	零件包装代码：	QFP
包装说明：	FQFP,	针数：	240
Reach Compliance Code：	unknown	ECCN代码：	3A991.A.2
HTS代码：	8542.31.00.01	风险等级：	5.7
具有ADC：	NO	地址总线宽度：	32
位大小：	32	最大时钟频率：	33 MHz
DAC 通道：	NO	DMA 通道：	YES
外部数据总线宽度：	32	JESD-30 代码：	S-CQFP-G240
长度：	31.305 mm	I/O 线路数量：	46
端子数量：	240	最高工作温度：	70 °C
最低工作温度：		PWM 通道：	NO
封装主体材料：	CERAMIC, METAL-SEALED COFIRED	封装代码：	FQFP
封装形状：	SQUARE	封装形式：	FLATPACK, FINE PITCH
认证状态：	Not Qualified	座面最大高度：	4.15 mm
速度：	33 MHz	最大压摆率：	327 mA
最大供电电压：	5 V	最小供电电压：	5 V
表面贴装：	YES	技术：	CMOS
温度等级：	COMMERCIAL	端子形式：	GULL WING
端子节距：	0.5 mm	端子位置：	QUAD
宽度：	31.305 mm	uPs/uCs/外围集成电路类型：	MICROCONTROLLER, RISC
Base Number Matches：	1

MC68MH360FE33 数据手册

Table of Contents

Paragraph

Number

Title

Page

Number

QUICC Memory Map

3.1

3.2

3.3

3.3.1

3.3.2

Dual-Port RAM Memory Map .................................................................. 3-2

CPM Sub-Module Base Addresses......................................................... 3-3

Internal Registers Memory Map .............................................................. 3-4

SIM Registers Memory Map.................................................................... 3-4

CPM Registers Memory Map .................................................................. 3-6

Section 4

Bus Operation

4.1

Bus Transfer Signals............................................................................... 4-2

Bus Control Signals................................................................................. 4-3

Function Codes (FC3–FC0) .................................................................... 4-3

Address Bus (A31–A0)............................................................................ 4-4

Address Strobe (AS) ............................................................................... 4-4

Data Bus (D31-D0).................................................................................. 4-4

Data Strobe (DS)..................................................................................... 4-4

Output Enable (OE)................................................................................. 4-4

Byte Write Enable (WE0, WE1, WE2, WE3)........................................... 4-4

Bus Cycle Termination Signals ............................................................... 4-5

Data transfer and size acknowledge (DSACK1 and DSACK0)............... 4-5

Bus Error (BERR).................................................................................... 4-5

Autovector (AVEC).................................................................................. 4-6

Data Transfer Mechanism....................................................................... 4-6

Dynamic Bus Sizing ................................................................................ 4-6

Misaligned Operands ............................................................................ 4-11

Effects of Dynamic Bus Sizing and Operand Misalignment .................. 4-19

Bus Operation ....................................................................................... 4-20

Synchronous Operation with DSACKx.................................................. 4-21

Fast Termination Cycles........................................................................ 4-21

Data Transfer Cycles............................................................................. 4-22

Read Cycle............................................................................................ 4-23

Write Cycle............................................................................................ 4-26

Read-Modify-Write Cycle ...................................................................... 4-28

CPU Space Cycles................................................................................ 4-31

Breakpoint Acknowledge Cycle............................................................. 4-31

LPSTOP Broadcast Cycle..................................................................... 4-35

Module Base Address Register (MBAR) Access .................................. 4-36

Interrupt Acknowledge Bus Cycles........................................................ 4-36

Interrupt Acknowledge Cycle—Terminated Normally............................ 4-36

Autovector Interrupt Acknowledge Cycle. ............................................. 4-38

Spurious Interrupt Cycle........................................................................ 4-40

Bus Exception Control Cycles............................................................... 4-41

Bus Errors ............................................................................................. 4-42

Retry Operation..................................................................................... 4-44

Halt Operation ....................................................................................... 4-46

Double Bus Fault................................................................................... 4-48

4.1.1

4.1.2

4.1.3

4.1.4

4.1.5

4.1.6

4.1.7

4.1.8

4.1.9

4.1.9.1

4.1.9.2

4.1.9.3

4.2

4.2.1

4.2.2

4.2.3

4.2.4

4.2.5

4.2.6

4.3

4.3.1

4.3.2

4.3.3

4.4

4.4.1

4.4.2

4.4.3

4.4.4

4.4.4.1

4.4.4.2

4.4.4.3

4.5

4.5.1

4.5.2

4.5.3

4.5.4

MOTOROLA

MC68360 USER’S MANUAL

iii

1...4 5 678 9 10...962

中文翻译

下载PDF

与MC68MH360FE33相关器件

型号	品牌	获取价格	描述	数据表
MC68MH360FE33E	MOTOROLA	获取价格	32-BIT, 33MHz, RISC MICROCONTROLLER, CQFP240, CERAMIC, QFP-240
MC68MH360RC25	MOTOROLA	获取价格	QUad Integrated Communications Controller Users Manual
MC68MH360RC25L	NXP	获取价格	4 CHANNEL(S), 10Mbps, LOCAL AREA NETWORK CONTROLLER, CPGA241, PGA-241
MC68MH360RC25L	MOTOROLA	获取价格	4 CHANNEL(S), 10Mbps, LOCAL AREA NETWORK CONTROLLER, CPGA241, PGA-241
MC68MH360RC25V	MOTOROLA	获取价格	QUad Integrated Communications Controller Users Manual
MC68MH360RC25V	NXP	获取价格	RISC MICROCONTROLLER, CPGA241, PGA-241
MC68MH360RC33	NXP	获取价格	RISC MICROCONTROLLER, CPGA241, PGA-241
MC68MH360RC33	MOTOROLA	获取价格	QUad Integrated Communications Controller Users Manual
MC68MH360RC33L	MOTOROLA	获取价格	4 CHANNEL(S), 10Mbps, LOCAL AREA NETWORK CONTROLLER, CPGA241, PGA-241
MC68MH360RC33L	NXP	获取价格	QUICC, 2SMC, 1SPI

与MC68MH360FE33相关文章

压敏电阻器在直流电路中的过压保护应用探讨
2024-06-07

2
电感耐压值及其与电感大小的关系
2024-06-07

5
CNY17F光耦合器：特性、应用、封装、引脚功能及替换型号解析
2024-06-07

4
DS1307资料解析：特性、引脚说明、替代推荐
2024-06-07

3

产品中心

服务支持

精选活动

关于我们

帮助中心

MC68MH360FE33

MC68MH360FE33 技术参数

MC68MH360FE33 数据手册

与MC68MH360FE33相关器件

与MC68MH360FE33相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

MC68MH360FE33

MC68MH360FE33 技术参数

MC68MH360FE33 数据手册

与MC68MH360FE33相关器件

与MC68MH360FE33相关文章

您还可以找

您在本页遇到什么问题？