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MC68MH360FE25V PDF预览

MC68MH360FE25V

更新时间: 2024-01-03 11:17:44
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 微控制器和处理器通信控制器外围集成电路时钟
页数 文件大小 规格书
962页 2727K
描述
QUad Integrated Communications Controller Users Manual

MC68MH360FE25V 技术参数

生命周期:Obsolete零件包装代码:QFP
包装说明:FQFP,针数:240
Reach Compliance Code:unknownHTS代码:8542.31.00.01
风险等级:5.7具有ADC:NO
地址总线宽度:32位大小:32
最大时钟频率:25 MHzDAC 通道:NO
DMA 通道:YES外部数据总线宽度:32
JESD-30 代码:S-CQFP-G240长度:31.305 mm
I/O 线路数量:46端子数量:240
最高工作温度:70 °C最低工作温度:
PWM 通道:NO封装主体材料:CERAMIC, METAL-SEALED COFIRED
封装代码:FQFP封装形状:SQUARE
封装形式:FLATPACK, FINE PITCH认证状态:Not Qualified
座面最大高度:4.15 mm速度:25 MHz
最大压摆率:250 mA最大供电电压:3.3 V
最小供电电压:3.3 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子形式:GULL WING端子节距:0.5 mm
端子位置:QUAD宽度:31.305 mm
uPs/uCs/外围集成电路类型:MICROCONTROLLER, RISCBase Number Matches:1

MC68MH360FE25V 数据手册

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Table of Contents  
Paragraph  
Number  
Title  
Page  
Number  
Section 1  
Introduction  
1.1  
1.2  
QUICC Key Features .............................................................................. 1-1  
QUICC Architecture Overview................................................................. 1-4  
CPU32+ Core.......................................................................................... 1-5  
System Integration Module (SIM60)........................................................ 1-5  
Communications Processor Module (CPM) ............................................ 1-6  
Upgrading Designs from the MC68302................................................... 1-6  
Architectural Approach............................................................................ 1-6  
Hardware Compatibility Issues................................................................ 1-7  
Software Compatibility Issues ................................................................. 1-7  
QUICC Glueless System Design............................................................. 1-8  
QUICC Serial Configurations .................................................................. 1-9  
QUICC Serial Configuration Examples ................................................. 1-16  
QUICC System Bus Configurations ...................................................... 1-17  
1.2.1  
1.2.2  
1.2.3  
1.3  
1.3.1  
1.3.2  
1.3.3  
1.4  
1.5  
1.6  
1.7  
Section 2  
Signal Descriptions  
2.1  
2.1.1  
2.1.1.1  
2.1.1.2  
2.1.2  
System Bus Signal Index ........................................................................ 2-1  
Address Bus............................................................................................ 2-1  
Address Bus (A27–A0)............................................................................ 2-1  
Address Bus (A31–A28).......................................................................... 2-1  
Function Codes (FC3–FC0) .................................................................... 2-5  
Data Bus.................................................................................................. 2-5  
Data Bus (D31–D16)............................................................................... 2-5  
Data Bus (D15–D0)................................................................................. 2-6  
Parity ....................................................................................................... 2-6  
Parity (PRTY0). ....................................................................................... 2-6  
Parity (PRTY1). ....................................................................................... 2-6  
Parity (PRTY2). ....................................................................................... 2-6  
Parity (PRTY3). ....................................................................................... 2-6  
Memory Controller................................................................................... 2-6  
Chip Select/Row Address Select (CS6–CS0/RAS6–RAS0) ................... 2-6  
Chip Select/Row Address Select/Interrupt Acknowledge (CS7/RAS7/IACK7).  
2.1.3  
2.1.3.1  
2.1.3.2  
2.1.4  
2.1.4.1  
2.1.4.2  
2.1.4.3  
2.1.4.4  
2.1.5  
2.1.5.1  
2.1.5.2  
2-6  
2.1.5.3  
1).  
Column Address Select/Interrupt Acknowledge (CAS3–CAS0/IACK6, 3, 2,  
2-7  
2.1.5.4  
2.1.6  
2.1.7  
2.1.7.1  
2.1.7.2  
2.1.7.3  
2.1.7.4  
Address Multiplex (AMUX). ..................................................................... 2-7  
Interrupt Request Level (IRQ7–IRQ1)..................................................... 2-7  
Bus Control Signals................................................................................. 2-7  
Data and Size Acknowledge (DSACK1–DSACK0). ................................ 2-8  
Autovector/Interrupt Acknowledge (AVEC/IACK5).................................. 2-8  
Address Strobe (AS). .............................................................................. 2-8  
Data Strobe (DS)..................................................................................... 2-8  
MOTOROLA  
MC68360 USER’S MANUAL  
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