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MC33909Q5AD PDF预览

MC33909Q5AD

更新时间： 2024-02-12 22:20:09
品牌 Logo 应用领域
恩智浦 - NXP /
页数 文件大小 规格书
94页 2482K
描述
System Basis Chip, 1 CAN, 4 LIN, 6 MSDI, 2A DC/DC, LV124, 5V/500mA LDO, LQFP-EP 48, Tray

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MC33909Q5AD 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active包装说明：LQFP-48
Reach Compliance Code：compliant风险等级：5.7
Base Number Matches：1

MC33909Q5AD 数据手册

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Document Number: MC33909  
Rev. 4.0, 8/2016  
NXP Semiconductors  
Advance Information  
System basis chip with DC/DC and  
multiple switch-to-ground interface  
33909  
This SMARTMOS IC integrates the common functionality of system basis chips  
with switch detection inputs. The device works as an advanced power  
management unit for the MCU and additional integrated circuits such as  
sensors, CAN transceivers, and eXtreme switches. It has one built-in enhanced  
high-speed CAN interface (ISO 11898-2 and -5), with local and bus failure  
diagnostics, protection and fail-safe operation mode, and includes four LINs,  
compatible with specification 2.1 and SAEJ2602-2.  
SYSTEM BASIS CHIP  
The IC starts operating when the VBATP (reverse battery protected) pin  
reaches 5.3 V maximum. The device requires a reverse blocking ultrafast or  
Schottky diode for operation. The VPRE supply operating in Buck/Boost mode  
allows functional operation of the IC from 2.5 V to 35 V on VBATP. The VPRE  
pin supplies the source voltage for the VDD, VAUX, CAN5V, and SG power  
rails.  
AD SUFFIX (PB-FREE)  
48 PIN LQFP-EP  
98ASA00737D  
Switch-to-ground inputs are available for switch detection and supply  
configurable pulsed wetting current, with low sustain current levels for  
improved thermal and power management. The IC can be programmed to  
wake-up when a change of state is detected on any input. The device also  
implements an innovative and advanced fail-safe state machine and concept  
solution.  
Applications  
• Front/rear body controllers  
• Gateway modules  
• Electric power steering  
• Power train  
Features  
• VDD rail (3.3 V or 5.0 V) operates down to 2.5 V on VBATP (provided by  
VPRE Buck/Boost)  
• VAUX rail (3.3 V or 5.0 V) capable of surviving short-to-battery (40 V)  
conditions  
• Low Q current operation for low-power sleep mode, typ. 125 μA  
• Secured SPI and advanced watchdog  
• SAFE_B pin for limp home mode  
• Six switch to GND inputs with selectable wake-up in change of state  
• Analog multiplexer  
VPRE VAUXE VAUXB  
VSW VPREGATE  
VAUX  
VDDE  
VBAT  
BOOT  
PI Filter  
VBAT_SMPS  
VDDB  
VDD  
VDD  
VBATP  
VBAT  
VBATSNS  
WDI  
SAFE_B  
AMUX  
SG0  
SG1  
SG2  
SG3  
SG4  
SG5  
RST_B  
INT_B  
MCU  
MOSI  
MISO  
SCLK  
CS_B  
SPI  
CANH  
CANL  
CAN Bus  
RXD_L0:RXD_L3  
TXD_L0:TXD_L3  
VBATP  
RXD_C  
TXD_C  
LIN_0  
LIN_1  
LIN_2  
LIN_3  
LIN Bus  
LIN Bus  
LIN Bus  
LIN Bus  
CAN5V  
GND LIN  
GND  
CANGND  
Figure 1. 33909AD simplified application diagram  
* This document contains certain information on a new product.  
Specifications and information herein are subject to change without notice.  
© 2016 NXP B.V.  
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