LANSDALE Semiconductor, Inc.
ML145554, ML145557, ML145564, ML145567
complementary outputs. The output of the second amplifier may be
high, the sign bit appears at the D output. The next seven rising
X
internally connected to the input of the transmit anti–aliasing filter by edges of BCLK clock out the remaining seven bits of the PCM
X
bringing the ANLB pin high. The power amplifiers can drive unbal-
anced 300 Ω loads or a balanced 600 Ω load; they may be powered
down independent of the rest of the chip by tying the VPI pin to
word. The D and TS outputs return to a high impedance state on
X X
the falling edge of the eighth bit clock or the falling edge of FS ,
X
whichever comes later. The receive PCM word is clocked into D on
R
V
.
the eight falling BCLK edges following an FS rising edge.
R R
BB
For Short Frame Sync operation, the frame sync pulses must be
one bit clock period long. On the first BCLK rising edge after the
MASTER CLOCKS
X
falling edge of BCLK has latched FS high, the D and TS out-
X
X
X
X
Since the codec–filter design has a single DAC architecture, only
one master clock is used. In normal operation (both frame syncs
puts are enabled and the sign bit is presented on D . The next seven
X
rising edges of BCLK clock out the remaining seven bits of the
X
clocking), the MCLK is used as the master clock, regardless of
PCM word; on the eighth BCLK falling edge, the D and TS
X X X
X
whether the MCLK /PDN pin is clocking or low. The same is true if outputs return to a high impedance state. On the second falling
R
the part is in transmit half–channel mode (FS clocking, FS held
BCLK edge following an FS rising edge, the receive sign bit is
R R
X
R
low). But if the codec–filter is in the receive half–channel mode, with clocked into D . The next seven BCLK falling edges clock in the
R
R
FS clocking and FS held low, MCLK is used for the internal
remaining seven bits of the receive PCM word.
Table 2 shows the coding format of the transmit and receive PCM
words.
R
X
R
master clock if it is clocking; if MCLK is low, then MCLK is still
R
X
used for the internal master clock. Since only one of the master
clocks isused at any given time, they need not be synchronous.
The master clock frequency must be 1.536 MHz, 1.544 MHz, or
2.048 MHz. The frequency that the codec–filter expects depends
upon whether the part is a Mu–Law or an A–Law part, and on the
HALF–CHANNEL MODES
In addition to the normal full–duplex operating mode, these
state of the BCLK /CLKSEL pin.The allowable options are shown
R
codec–filters can operate in both transmit and receive half–channel
In Table 1. When a level (rather than a clock) is provided for
modes. Transmit half–channel mode is entered by holding FS low.
R
BCLK /CLKSEL, BCLK is used as the bit clock for both transmit The VF O output goes to analog ground but remains in a low imped-
R
X
R
and receive.
ance state (to facilitate a hybrid interface); PCM data at D is
R
ignored. Holding FS low while clocking FSR puts these devices in
X
the receive half–channel mode. In this state, the transmit input oper-
ational amplifier continues to operate, but the rest of the transmit cir-
Table 1. Master Clock Frequency Determination
Master Clock Frequency Expected
cuitry is disabled; the D and TS outputs remain in a high imped-
X
X
BCLK /CLKSEL
R
ML145554/64
ML145557/67
ance state. MCLK is used as the internal master clock if it is clock-
R
ing. If MCLK is not clocking, then MCLK is used for the internal
Clocked, 1, or Open
1.536 MHz
1.544 MHz
2.048 MHz
R
X
master clock, but in that case it should be synchronous with FS . If
R
BCLK is not clocking, BCLK will be used for the receive data,
R
X
0
2.048 MHz
1.536 MHz
1.544 MHz
just as in the full–channel operating mode. In receive half–channel
mode only, the length ofthe FS pulse is used to determine whether
R
Short Frame Sync or Long Frame Sync timing is used at D .
R
FRAME SYNCS AND DIGITAL I/O
POWER–DOWN
These codec–filters can accommodate both of the industry standard
timing formats. The Long Frame Sync mode isused by Lansdale’s
ML145500 family of codec–filters and the UDLT family of digital
Holding both FS and FS low causes the part to go into the
X
R
power–down state. Power–down occurs approximately 2 ms after the
loop transceivers. The Short Frame Sync mode is compatible with the last frame sync pulse is received. An alternative way to put these
IDL (Interchip Digital Link) serial format used in Motorola and devices in power–down is to hold the MCLK /PDN pin high. When
R
Lansdale’s ISDN family and by other companies in their telecommu- the chip is powered down, the D , TS , and GS outputs are high
X
X
X
nication devices. These codec–filters use the length of the transmit
impedance, the VF O, VPO–, and VPO+ operational amplifiers are
R
frame sync (FS ) to determine the timing format for both transmit
X
biased with a trickle current so that their respective outputs remain
stable at analog ground. To return the chip to the power–up state,
and receive unless the part is operating in the receive half–channel
mode.
MCLK /PDN must be low or clocking and at least one of the frame
R
In the Long Frame Sync mode, the frame sync pulses must be at
sync pulses must be present. The D and TS outputs will remain in
X X
least three bit clock periods long. The D and TS outputs are
a high–impedance state until the second FS pulse after power–up.
X
X
X
X
enabled by the logical ANDing of FS and BCLK ; when both are
X
Table 2. PCM Data Format
Mu–Law (ML145554/64)
A–Law (ML145557/67)
Level
+ Full Scale
+ Zero
Sign Bit
Chord Bits
0 0 0
Step Bits
0 0 0 0
1 1 1 1
1 1 1 1
0 0 0 0
Sign Bit
Chord Bits
0 1 0
Step Bits
1 0 1 0
0 1 0 1
0 1 0 1
1 0 1 0
1
1
0
0
1
1
0
0
1 1 1
1 0 1
– Zero
1 1 1
1 0 1
– Full Scale
0 0 0
0 1 0
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