The MC14555B and MC14556B are constructed with
complementary MOS (CMOS) enhancement mode devices. Each
Decoder/Demultiplexer has two select inputs (A and B), an active low
Enable input (E), and four mutually exclusive outputs (Q0, Q1, Q2,
Q3). The MC14555B has the selected output go to the “high” state,
and the MC14556B has the selected output go to the “low” state.
Expanded decoding such as binary–to–hexadecimal (1–of–16), etc.,
can be achieved by using other MC14555B or MC14556B devices.
Applications include code conversion, address decoding, memory
selection control, and demultiplexing (using the Enable input as a data
input) in digital data transmission systems.
http://onsemi.com
MARKING
DIAGRAMS
16
PDIP–16
P SUFFIX
CASE 648
MC1455XBCP
AWLYYWW
1
• Diode Protection on All Inputs
16
• Active High or Active Low Outputs
• Expandable
• Supply Voltage Range = 3.0 Vdc to 18 Vdc
• All Outputs Buffered
SOIC–16
D SUFFIX
CASE 751B
1455XB
AWLYWW
1
16
• Capable of Driving Two Low–Power TTL Loads or One Low–Power
Schottky TTL Load Over the Rated Temperature Range
SOEIAJ–16
F SUFFIX
CASE 966
MC1455XB
AWLYWW
1
X
A
= Specific Device Code
= Assembly Location
MAXIMUM RATINGS (Voltages Referenced to V ) (Note 2.)
SS
Symbol
Parameter
Value
Unit
V
WL or L = Wafer Lot
YY or Y = Year
WW or W = Work Week
V
DD
DC Supply Voltage Range
–0.5 to +18.0
V , V
in out
Input or Output Voltage Range
(DC or Transient)
–0.5 to V + 0.5
V
DD
ORDERING INFORMATION
I , I
Input or Output Current
(DC or Transient) per Pin
±10
mA
in out
Device
Package
PDIP–16
SOIC–16
Shipping
P
D
Power Dissipation,
per Package (Note 3.)
500
mW
MC14555BCP
MC14555BD
2000/Box
48/Rail
T
A
Ambient Temperature Range
Storage Temperature Range
–55 to +125
–65 to +150
260
°C
°C
°C
T
stg
MC14555BDR2
SOIC–16 2500/Tape & Reel
T
L
Lead Temperature
(8–Second Soldering)
MC14555BF
SOEIAJ–16
SOEIAJ–16
PDIP–16
See Note 1.
See Note 1.
2000/Box
48/Rail
MC14555BFEL
MC14556BCP
MC14556BD
2. Maximum Ratings are those values beyond which damage to the device
may occur.
3. Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/ C From 65 C To 125 C
SOIC–16
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
MC14556BDR2
SOIC–16 2500/Tape & Reel
MC14556BF
SOEIAJ–16
SOEIAJ–16
See Note 1.
See Note 1.
high–impedancecircuit. For proper operation, V and V should be constrained
in
out
MC14556BFEL
to the range V
(V or V
)
V
DD
.
SS
in
out
Unused inputs must always be tied to an appropriate logic voltage level (e.g.,
either V or V ). Unused outputs must be left open.
1. For ordering information on the EIAJ version of
the SOIC packages, please contact your local
ON Semiconductor representative.
SS
DD
Semiconductor Components Industries, LLC, 2000
1
Publication Order Number:
March, 2000 – Rev. 3
MC14555B/D