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MC14554BALD PDF预览

MC14554BALD

更新时间: 2024-10-28 13:11:15
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA /
页数 文件大小 规格书
6页 173K
描述
Multiplier, 4000/14000/40000 Series, 2-Bit, CMOS, CDIP16, 620-09

MC14554BALD 技术参数

是否Rohs认证:不符合生命周期:Obsolete
包装说明:DIP,Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.92
Is Samacsys:N其他特性:CASCADABLE
系列:4000/14000/40000JESD-30 代码:R-GDIP-T16
JESD-609代码:e0长度:19.3 mm
负载电容(CL):50 pF逻辑集成电路类型:MULTIPLIER
位数:2功能数量:1
端子数量:16最高工作温度:125 °C
最低工作温度:-55 °C封装主体材料:CERAMIC, GLASS-SEALED
封装代码:DIP封装形状:RECTANGULAR
封装形式:IN-LINE峰值回流温度(摄氏度):NOT SPECIFIED
传播延迟(tpd):1700 ns认证状态:Not Qualified
座面最大高度:4.19 mm最大供电电压 (Vsup):18 V
最小供电电压 (Vsup):3 V标称供电电压 (Vsup):5 V
表面贴装:NO技术:CMOS
温度等级:MILITARY端子面层:Tin/Lead (Sn/Pb)
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:7.62 mmBase Number Matches:1

MC14554BALD 数据手册

 浏览型号MC14554BALD的Datasheet PDF文件第2页浏览型号MC14554BALD的Datasheet PDF文件第3页浏览型号MC14554BALD的Datasheet PDF文件第4页浏览型号MC14554BALD的Datasheet PDF文件第5页浏览型号MC14554BALD的Datasheet PDF文件第6页 
SEMICONDUCTOR TECHNICAL DATA  
L SUFFIX  
CERAMIC  
CASE 620  
The MC14554B 2 x 2–bit parallel binary multiplier is constructed with  
complementary MOS (CMOS) enhancement mode devices. The multiplier  
can perform the multiplication of two binary numbers and simultaneously add  
two other binary numbers to the product. The MC14554B has two  
multiplicand inputs (X0 and X1), two multiplier inputs (Y0 and Y1), five  
cascading or adding inputs (K0, K1, M0, M1, and M2), and five sum and  
carry outputs (S0, S1, S2, C1 [S3], and C0). The basic multiplier can be  
expanded into a straightforward m–bit by n–bit parallel multiplier without  
additional logic elements.  
P SUFFIX  
PLASTIC  
CASE 648  
D SUFFIX  
SOIC  
Application areas include arithmetic processing (multiplying/adding,  
obtaining square roots, polynomial evaluation, obtaining reciprocals, and  
dividing), Fast Fourier Transform processing, digital filtering, communica-  
tions (convolution and correlation), and process and machine controls.  
CASE 751B  
ORDERING INFORMATION  
MC14XXXBCP  
MC14XXXBCL  
MC14XXXBD  
Plastic  
Ceramic  
SOIC  
Diode Protection on All Inputs  
All Outputs Buffered  
Straight–forward m–Bit By n–Bit Expansion  
No Additional Logic Elements Needed for Expansion  
Multiplies and Adds Simultaneously  
T
A
= – 55° to 125°C for all packages.  
This device contains protection circuitry to  
guard against damage due to high static  
voltages or electric fields. However, pre-  
cautions must be taken to avoid applications of  
any voltage higher than maximum rated volt-  
ages to this high–impedance circuit. For proper  
Positive Logic Design  
Supply Voltage Range = 3.0 Vdc to 18 Vdc  
Capable of Driving Two Low–Power TTL Loads or One Low–Power  
Schottky TTL Load Over the Rated Temperature Range  
MAXIMUM RATINGS* (Voltages Referenced to V  
)
SS  
operation, V and V  
should be constrained  
in out  
Symbol  
Parameter  
DC Supply Voltage  
Value  
Unit  
V
to the range V  
(V or V  
SS in out  
)
V
DD  
.
Unused inputs must always be tied to an  
appropriate logic voltage level (e.g., either V  
V
– 0.5 to + 18.0  
DD  
V , V  
SS  
Input or Output Voltage (DC or Transient)  
– 0.5 to V  
DD  
+ 0.5  
V
or V ). Unused outputs must be left open.  
DD  
in out  
I , I  
in out  
Input or Output Current (DC or Transient),  
per Pin  
± 10  
mA  
P
D
Power Dissipation, per Package†  
Storage Temperature  
500  
– 65 to + 150  
260  
mW  
C
EQUATIONS  
S = (X x Y) + K + M  
T
stg  
Where:  
T
L
Lead Temperature (8–Second Soldering)  
C
x Means Arithmetic Times.  
+ Means Arithmetic Plus.  
S = S3 S2 S1 S0, X = X1X0, Y = Y1Y0,  
K = K1 K0, M = M1 M0 (Binary Numbers).  
* Maximum Ratings are those values beyond which damage to the device may occur.  
Temperature Derating:  
Plastic “P and D/DW” Packages: – 7.0 mW/ C From 65 C To 125 C  
Ceramic “L” Packages: – 12 mW/ C From 100 C To 125 C  
Example:  
Given: X = 2(1), Y = 3(11)  
K = 1(01), M = 2(10)  
PIN ASSIGNMENT  
Then: S = (2 x 3) + 1 + 2 = 9  
S = (10 x 11) + 01 + 10 = 1001  
Y1  
M0  
1
2
16  
15  
V
DD  
Y0  
X0  
X1  
K0  
S0  
K1  
S1  
NOTE: C0 connected to M2 for this size  
multiplier. See general expansion  
diagram for other size multipliers.  
M1  
3
4
5
6
7
8
14  
13  
12  
11  
10  
9
C0  
M2  
C1 (S3)  
S2  
V
SS  
REV 3  
1/94  
Motorola, Inc. 1995  

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