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MC14554BALD PDF预览

MC14554BALD

更新时间: 2024-02-08 15:55:09
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA /
页数 文件大小 规格书
6页 173K
描述
Multiplier, 4000/14000/40000 Series, 2-Bit, CMOS, CDIP16, 620-09

MC14554BALD 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
Reach Compliance Code:unknown风险等级:5.92
JESD-30 代码:R-XDIP-T16JESD-609代码:e0
端子数量:16最高工作温度:125 °C
最低工作温度:-55 °C封装主体材料:CERAMIC
封装代码:DIP封装等效代码:DIP16,.3
封装形状:RECTANGULAR封装形式:IN-LINE
电源:5/15 V认证状态:Not Qualified
筛选级别:MIL-STD-883 Class B (Modified)子类别:DSP Peripherals
表面贴装:NO技术:CMOS
温度等级:MILITARY端子面层:Tin/Lead (Sn/Pb)
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUALuPs/uCs/外围集成电路类型:DSP PERIPHERAL, MULTIPLIER
Base Number Matches:1

MC14554BALD 数据手册

 浏览型号MC14554BALD的Datasheet PDF文件第1页浏览型号MC14554BALD的Datasheet PDF文件第2页浏览型号MC14554BALD的Datasheet PDF文件第4页浏览型号MC14554BALD的Datasheet PDF文件第5页浏览型号MC14554BALD的Datasheet PDF文件第6页 
SWITCHING CHARACTERISTICS* (C = 50 pF, T = 25 C)  
L
A
Characteristic  
Symbol  
V
DD  
Min  
Typ #  
Max  
Unit  
Output Rise and Fall Time  
t
t
,
ns  
TLH  
t
t
t
, t  
= (1.5 ns/pF) C + 25 ns  
= (0.75 ns/pF) C + 12.5 ns  
= (0.55 ns/pF) C + 9.5 ns  
5.0  
10  
15  
100  
50  
40  
200  
100  
80  
TLH THL  
L
L
L
THL  
, t  
TLH THL  
, t  
TLH THL  
Propagation Delay Time  
K0 to C0  
t
t
,
ns  
PLH  
PHL  
t
t
t
, t  
= (1.7 ns/pF) C + 185 ns  
= (0.66 ns/pF) C + 82 ns  
= (0.5 ns/pF) C + 60 ns  
L
5.0  
10  
15  
270  
115  
85  
675  
290  
215  
PLH PHL  
L
L
, t  
PLH PHL  
, t  
PLH PHL  
M0 to S2  
t
t
t
, t  
= (1.7 ns/pF) C + 595 ns  
5.0  
10  
15  
680  
280  
210  
1700  
750  
570  
PLH PHL  
L
, t  
= (0.66 ns/pF) C + 247 ns  
L
PLH PHL  
, t  
PLH PHL  
= (0.5 ns/pF) C + 185 ns  
L
* The formulas given are for the typical characteristics only at 25 C.  
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.  
20 ns  
20 ns  
V
V
V
V
DD  
SS  
OH  
OL  
90%  
10%  
50%  
INPUT  
K0 OR M0  
20 ns  
20 ns  
t
t
PHL  
PLH  
90%  
V
V
50%  
DD  
10%  
90%  
50%  
10%  
OUTPUT  
C0 OR S2  
ALL INPUTS  
SS  
t
t
THL  
(50% DUTY CYCLE)  
TLH  
1
2f  
For K0 to C0:  
Inputs X0, X1, Y0, Y1, K1, and M2 low, and inputs  
M0 and M1 high.  
V
V
OH  
ANY OUTPUT  
OL  
For M0 to S2:  
(50% DUTY CYCLE)  
All outputs connected to respective  
loads. f = system clock frequency  
Inputs X1, Y1, and K0 low, and inputs X0, Y0,  
K1, M1, and M2 high.  
C
L
Figure 1. Dynamic Power Dissipation  
Waveforms  
Figure 2. Dynamic Signal Waveforms  
LOGIC DIAGRAM  
M1  
M
Y1  
M0  
Y0  
15  
3
1
2
Y
M
Y
14  
12  
X0  
K0  
X
X
K
MULTIPLIER  
CELL  
MULTIPLIER  
CELL  
4
5
MULTIPLIER CELL  
C
C
C0  
M2  
K
S
S
S
C
M
Y
X
K
L
M
Y
M
Y
13  
10  
X1  
K1  
X
K
X
K
MULTIPLIER  
CELL  
MULTIPLIER  
CELL  
C
C
S
S
6
7
9
11  
C1(S3)  
S2  
S1  
S0  
MOTOROLA CMOS LOGIC DATA  
MC14554B  
3

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