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MC14543B_06

更新时间： 2024-11-04 04:59:27
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安森美 - ONSEMI 解码器驱动器锁存器
页数 文件大小 规格书
8页 112K
描述
BCD−to−Seven Segment Latch/Decoder/Driver for Liquid Crystals

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MC14543B_06 数据手册

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MC14543B  
BCD−to−Seven Segment  
Latch/Decoder/Driver for  
Liquid Crystals  
The MC14543B BCD−to−seven segment latch/decoder/driver is  
designed for use with liquid crystal readouts, and is constructed with  
complementary MOS (CMOS) enhancement mode devices. The  
circuit provides the functions of a 4−bit storage latch and an 8421  
BCD−to−seven segment decoder and driver. The device has the  
capability to invert the logic levels of the output combination. The  
phase (Ph), blanking (BI), and latch disable (LD) inputs are used to  
reverse the truth table phase, blank the display, and store a BCD code,  
respectively. For liquid crystal (LC) readouts, a square wave is applied  
to the Ph input of the circuit and the electrically common backplane of  
the display. The outputs of the circuit are connected directly to the  
segments of the LC readout. For other types of readouts, such as  
light−emitting diode (LED), incandescent, gas discharge, and  
fluorescent readouts, connection diagrams are given on this data sheet.  
Applications include instrument (e.g., counter, DVM etc.) display  
driver, computer/calculator display driver, cockpit display driver, and  
various clock, watch, and timer uses.  
http://onsemi.com  
MARKING  
DIAGRAMS  
16  
PDIP−16  
MC14543BCP  
AWLYYWWG  
P SUFFIX  
CASE 648  
1
1
16  
SOIC−16  
D SUFFIX  
CASE 751B  
14543BG  
AWLYWW  
1
1
Features  
• Latch Storage of Code  
• Blanking Input  
16  
SOEIAJ−16  
F SUFFIX  
CASE 966  
MC14543B  
ALYWG  
• Readout Blanking on All Illegal Input Combinations  
1
1
• Direct LED (Common Anode or Cathode) Driving Capability  
• Supply Voltage Range = 3.0 V to 18 V  
• Capable of Driving 2 Low−power TTL Loads, 1 Low−power Schottky  
TTL Load or 2 HTL Loads Over the Rated Temperature Range  
• Pin−for−Pin Replacement for CD4056A (with Pin 7 Tied to V ).  
• Chip Complexity: 207 FETs or 52 Equivalent Gates  
• Pb−Free Packages are Available*  
A
= Assembly Location  
WL, L = Wafer Lot  
YY, Y = Year  
WW, W = Work Week  
SS  
G
= Pb−Free Package  
ORDERING INFORMATION  
MAXIMUM RATINGS (Voltages Referenced to V  
)
SS  
See detailed ordering and shipping information in the package  
dimensions section on page 2 of this data sheet.  
Parameter  
Symbol  
Value  
−0.5 to +18.0  
Unit  
V
DC Supply Voltage Range  
V
DD  
Input Voltage Range, All Inputs  
DC Input Current per Pin  
V
−0.5 to V +0.5  
V
in  
DD  
This device contains protection circuitry to guard  
against damage due to high static voltages or electric  
fields. However, precautions must be taken to avoid  
applications of any voltage higher than maximum rated  
voltages to this high−impedance circuit. For proper  
I
10  
mA  
mW  
°C  
in  
Power Dissipation per Package (Note 1)  
Operating Temperature Range  
Storage Temperature Range  
P
500  
D
T
A
−55 to +125  
−65 to +150  
operation, V and V should be constrained to the  
in  
out  
T
stg  
°C  
range V v (V or V ) v V  
.
DD  
SS  
in  
out  
Maximum Continuous Output Drive  
Current (Source or Sink)  
I
I
10  
mA  
OHmax  
OLmax  
Unused inputs must always be tied to an appropriate  
(per Output)  
logic voltage level (e.g., either V or V ). Unused  
SS  
DD  
outputs must be left open.  
Maximum Continuous Output Power  
(Source or Sink) (Note 2)  
P
P
70  
mW  
OHmax  
OLmax  
(per Output)  
Stresses exceeding Maximum Ratings may damage the device. Maximum  
Ratings are stress ratings only. Functional operation above the Recommended  
Operating Conditions is not implied. Extended exposure to stresses above the  
Recommended Operating Conditions may affect device reliability.  
1. Temperature Derating: Plastic “P and D/DW”  
*For additional information on our Pb−Free strategy  
and soldering details, please download the  
ON Semiconductor Soldering and Mounting  
Techniques Reference Manual, SOLDERRM/D.  
Packages: – 7.0 mW/_C From 65_C To 125_C  
2. P  
= I  
(V − V ) and P  
= I (V − V  
)
SS  
OHmax  
OH  
OH  
DD  
OLmax  
OL  
OL  
©
Semiconductor Components Industries, LLC, 2006  
1
Publication Order Number:  
June, 2006 − Rev. 6  
MC14543B/D  
 
12345678

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