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MC14538BDWR2G PDF预览

MC14538BDWR2G

更新时间： 2024-02-26 14:41:17
品牌 Logo 应用领域
安森美 - ONSEMI 振荡器预分频器多谐振动器逻辑集成电路光电二极管时钟
页数 文件大小 规格书
12页 151K
描述
Dual Precision Retriggerable/Resettable Monostable Multivibrator

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MC14538BDWR2G 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：SOIC
包装说明：SOP, SOP16,.4针数：16
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01Factory Lead Time：7 weeks
风险等级：0.85系列：4000/14000/40000
JESD-30 代码：R-PDSO-G16JESD-609代码：e3
长度：10.3 mm逻辑集成电路类型：MONOSTABLE MULTIVIBRATOR
湿度敏感等级：3数据/时钟输入次数：2
功能数量：2端子数量：16
最高工作温度：125 °C最低工作温度：-55 °C
输出极性：COMPLEMENTARY封装主体材料：PLASTIC/EPOXY
封装代码：SOP封装等效代码：SOP16,.4
封装形状：RECTANGULAR封装形式：SMALL OUTLINE
峰值回流温度（摄氏度）：260电源：5/15 V
传播延迟（tpd）：600 ns认证状态：Not Qualified
座面最大高度：2.65 mm子类别：Prescaler/Multivibrators
最大供电电压 (Vsup)：18 V最小供电电压 (Vsup)：3 V
标称供电电压 (Vsup)：5 V表面贴装：YES
技术：CMOS温度等级：MILITARY
端子面层：Tin (Sn)端子形式：GULL WING
端子节距：1.27 mm端子位置：DUAL
处于峰值回流温度下的最长时间：40宽度：7.5 mm
Base Number Matches：1

MC14538BDWR2G 数据手册

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MC14538B  
Dual Precision  
Retriggerable/Resettable  
Monostable Multivibrator  
The MC14538B is a dual, retriggerable, resettable monostable  
multivibrator. It may be triggered from either edge of an input pulse,  
and produces an accurate output pulse over a wide range of widths, the  
duration and accuracy of which are determined by the external timing  
components, C and R . Output Pulse Width T = R @ C (secs)  
http://onsemi.com  
MARKING  
DIAGRAMS  
X
X
X
X
R = W  
X
16  
1
PDIP−16  
P SUFFIX  
CASE 648  
C = Farads  
X
MC14538BCP  
AWLYYWWG  
Features  
• Unlimited Rise and Fall Time Allowed on the A Trigger Input  
• Pulse Width Range = 10 ms to 10 s  
• Latched Trigger Inputs  
• Separate Latched Reset Inputs  
• 3.0 Vdc to 18 Vdc Operational Limits  
• Triggerable from Positive (A Input) or Negative−Going Edge (B−Input)  
• Capable of Driving Two Low−Power TTL Loads or One Low−Power  
Schottky TTL Load Over the Rated Temperature Range  
16  
SOIC−16  
D SUFFIX  
CASE 751B  
14538BG  
AWLYWW  
1
16  
SOIC−16  
DW SUFFIX  
CASE 751G  
• Pin−for−pin Compatible with MC14528B and CD4528B (CD4098)  
14538BG  
AWLYYWW  
• Use the MC54/74HC4538A for Pulse Widths Less Than 10 ms with  
Supplies Up to 6 V  
1
• Pb−Free Packages are Available*  
MAXIMUM RATINGS (Voltages Referenced to V  
)
SS  
16  
1
Symbol  
Parameter  
Value  
−0.5 to +18.0  
Unit  
V
14  
538B  
ALYW  
TSSOP−16  
DT SUFFIX  
CASE 948F  
V
DC Supply Voltage Range  
DD  
V , V  
in out  
Input or Output Voltage Range  
(DC or Transient)  
−0.5 to V + 0.5  
V
DD  
I , I  
in out  
Input or Output Current  
(DC or Transient) per Pin  
10  
mA  
16  
P
T
Power Dissipation, per Package  
(Note 1)  
500  
mW  
D
SOEIAJ−16  
F SUFFIX  
CASE 966  
MC14538B  
ALYWG  
Operating Temperature Range  
Storage Temperature Range  
−55 to +125  
−65 to +150  
260  
°C  
°C  
°C  
A
1
T
stg  
A
WL, L  
YY, Y  
= Assembly Location  
= Wafer Lot  
= Year  
T
Lead Temperature  
(8−Second Soldering)  
L
Maximum ratings are those values beyond which device damage can occur.  
Maximum ratings applied to the device are individual stress limit values (not  
normal operating conditions) and are not valid simultaneously. If these limits are  
exceeded, device functional operation is not implied, damage may occur and  
reliability may be affected.  
WW, W = Work Week  
G
= Pb−Free Indicator  
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 2 of this data sheet.  
1. Temperature Derating:  
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C  
This device contains protection circuitry to guard against damage due to high  
static voltages or electric fields. However, precautions must be taken to avoid  
applications of any voltage higher than maximum rated voltages to this  
high−impedance circuit. For proper operation, V and V should be constrained  
in  
out  
*For additional information on our Pb−Free strategy  
and soldering details, please download the  
ON Semiconductor Soldering and Mounting  
Techniques Reference Manual, SOLDERRM/D.  
to the range V v (V or V ) v V  
.
DD  
SS  
in  
out  
Unused inputs must always be tied to an appropriate logic voltage level  
(e.g., either V or V ). Unused outputs must be left open.  
SS  
DD  
©
Semiconductor Components Industries, LLC, 2005  
1
Publication Order Number:  
August, 2005 − Rev. 7  
MC14538B/D  
 
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