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MC145402L PDF预览

MC145402L

更新时间: 2024-11-22 22:58:11
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 解码器编解码器电信集成电路电信电路
页数 文件大小 规格书
16页 137K
描述
Serial 13-Bit Linear Codec(A/D and D/A)

MC145402L 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:DIP包装说明:DIP, DIP16,.3
针数:16Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.92
Is Samacsys:N压伸定律:MU-LAW
滤波器:NOJESD-30 代码:R-GDIP-T16
JESD-609代码:e0长度:19.3 mm
线性编码:13-BIT负电源额定电压:-5 V
功能数量:1端子数量:16
工作模式:SYNCHRONOUS最高工作温度:70 °C
最低工作温度:封装主体材料:CERAMIC, GLASS-SEALED
封装代码:DIP封装等效代码:DIP16,.3
封装形状:RECTANGULAR封装形式:IN-LINE
峰值回流温度(摄氏度):NOT SPECIFIED电源:5 V
认证状态:Not Qualified座面最大高度:4.19 mm
子类别:Codecs标称供电电压:5 V
表面贴装:NO技术:CMOS
电信集成电路类型:LINEAR CODEC温度等级:COMMERCIAL
端子面层:TIN LEAD端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:7.62 mm
Base Number Matches:1

MC145402L 数据手册

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Order this document  
by MC145402/D  
SEMICONDUCTOR TECHNICAL DATA  
Advance Information  
16  
L SUFFIX  
CERAMIC PACKAGE  
CASE 620  
1
The MC145402 is a 13–bit linear monotonic digital–to–analog and analog–  
to–digital converter implemented in a single silicon–gate CMOS IC. Potential  
applications include analog interface for Digital Signal Processor (DSP)  
applications, high speed modems, telephone systems, SONAR, Adaptive  
Differential Pulse Code Modulation (ADPCM) converters, echo cancellers,  
repeaters, voice synthesizers, and music synthesizers.  
ORDERING INFORMATION  
MC145402L  
Ceramic Package  
60 dB Signal–to–(Noise Plus Distortion) Ratio Typical  
On–Chip Precision Voltage Reference  
Serial Data Ports  
Two’s Complement Coding  
± 5 V Supply Operation  
Sample Rates from 100 Hz to 16 kHz (Both A/D and D/A), 100 Hz to  
21.3 kHz (A/D Only), and 100 Hz to 64 kHz (D/A Only)  
Input Sample and Hold Provided On–Chip  
5 V CMOS Inputs; Outputs Capable of Driving Two LSTTL Loads  
Available in a 16–Pin DIP  
PIN ASSIGNMENT  
V
DD  
16  
15  
14  
13  
12  
11  
10  
9
V
1
2
3
4
5
6
7
8
AG  
A
RDD  
out  
A
RCE  
RDC  
in  
PDI  
TDC  
TDD  
TDE  
CCI  
MSI  
TDF  
Low Power Consumption: 50 mW Typical, 1 mW Power–Down  
V
V
DG  
SS  
BLOCK DIAGRAM  
BANDGAP VOLTAGE  
REFERENCE  
15  
RDD  
13  
14  
RECEIVE  
SHIFT  
REGISTER  
2
RDC  
RCE  
SAMPLE  
AND HOLD  
D/A  
CONVERTER  
DATA  
SELECTOR  
RECEIVE  
LATCH  
A
out  
7
10  
12  
TDF  
SUCCESSIVE  
APPROXIMATION  
REGISTER  
TRANSMIT  
SHIFT  
REGISTER  
3
SAMPLE  
AND HOLD  
COMPARATOR/  
OP AMP  
TRANSMIT  
LATCH  
A
TDE  
TDC  
in  
11  
TDD  
SEQUENCE  
CONTROLLER  
6
5
4
16  
8
1
9
MSI CCI PDI  
V
V
V
V
DG  
DD  
SS  
AG  
This document contains information on a new product. Specifications and information herein are subject to change without notice.  
Motorola, Inc. 1995  

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