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MC14538BD PDF预览

MC14538BD

更新时间： 2024-02-17 06:03:55
品牌 Logo 应用领域
安森美 - ONSEMI 振荡器预分频器多谐振动器逻辑集成电路光电二极管时钟
页数 文件大小 规格书
12页 289K
描述
Dual Precision Retiggerable/Resettable Monostable Multivibrator

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MC14538BD 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Obsolete零件包装代码：SOIC
包装说明：SOP, SOP16,.3针数：16
Reach Compliance Code：compliantHTS代码：8542.39.00.01
Factory Lead Time：1 week风险等级：8.16
系列：4000/14000/40000JESD-30 代码：R-PDSO-G16
JESD-609代码：e4长度：10.2 mm
逻辑集成电路类型：MONOSTABLE MULTIVIBRATOR湿度敏感等级：3
数据/时钟输入次数：2功能数量：2
端子数量：16最高工作温度：125 °C
最低工作温度：-55 °C输出极性：COMPLEMENTARY
封装主体材料：PLASTIC/EPOXY封装代码：SOP
封装等效代码：SOP16,.3封装形状：RECTANGULAR
封装形式：SMALL OUTLINE峰值回流温度（摄氏度）：260
电源：5/15 V传播延迟（tpd）：600 ns
认证状态：Not Qualified座面最大高度：2.05 mm
子类别：Prescaler/Multivibrators最大供电电压 (Vsup)：18 V
最小供电电压 (Vsup)：3 V标称供电电压 (Vsup)：5 V
表面贴装：YES技术：CMOS
温度等级：MILITARY端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：GULL WING端子节距：1.27 mm
端子位置：DUAL处于峰值回流温度下的最长时间：40
宽度：5.275 mmBase Number Matches：1

MC14538BD 数据手册

 浏览型号MC14538BD的Datasheet PDF文件第2页浏览型号MC14538BD的Datasheet PDF文件第3页浏览型号MC14538BD的Datasheet PDF文件第4页浏览型号MC14538BD的Datasheet PDF文件第5页浏览型号MC14538BD的Datasheet PDF文件第6页浏览型号MC14538BD的Datasheet PDF文件第7页 
The MC14538B is a dual, retriggerable, resettable monostable  
multivibrator. It may be triggered from either edge of an input pulse,  
and produces an accurate output pulse over a wide range of widths, the  
duration and accuracy of which are determined by the external timing  
http://onsemi.com  
MARKING  
DIAGRAMS  
components, C and R .  
X
X
16  
PDIP–16  
P SUFFIX  
CASE 648  
Output Pulse Width = (Cx) (Rx) where:  
Rx is in k  
Cx is in F  
MC14538BCP  
AWLYYWW  
1
16  
• Unlimited Rise and Fall Time Allowed on the A Trigger Input  
• Pulse Width Range = 10 µs to 10 s  
• Latched Trigger Inputs  
SOIC–16  
D SUFFIX  
CASE 751B  
14538B  
AWLYWW  
1
16  
• Separate Latched Reset Inputs  
• 3.0 Vdc to 18 Vdc Operational Limits  
• Triggerable from Positive (A Input) or Negative–Going Edge  
(B–Input)  
TSSOP–16  
DT SUFFIX  
CASE 948F  
14  
538B  
ALYW  
1
16  
• Capable of Driving Two Low–power TTL Loads or One Low–power  
Schottky TTL Load Over the Rated Temperature Range  
• Pin–for–pin Compatible with MC14528B and CD4528B (CD4098)  
14538B  
SOIC–16  
DW SUFFIX  
CASE 751G  
AWLYYWW  
• Use the MC54/74HC4538A for Pulse Widths Less Than 10 µs with  
1
Supplies Up to 6 V.  
16  
SOEIAJ–16  
F SUFFIX  
CASE 966  
MC14538B  
AWLYWW  
MAXIMUM RATINGS (Voltages Referenced to V ) (Note 2.)  
SS  
Symbol  
Parameter  
Value  
Unit  
V
1
A
= Assembly Location  
V
DD  
DC Supply Voltage Range  
–0.5 to +18.0  
WL or L = Wafer Lot  
YY or Y = Year  
WW or W = Work Week  
V , V  
in out  
Input or Output Voltage Range  
(DC or Transient)  
–0.5 to V + 0.5  
V
DD  
I , I  
in out  
Input or Output Current  
(DC or Transient) per Pin  
±10  
mA  
ORDERING INFORMATION  
Device  
Package  
PDIP–16  
SOIC–16  
Shipping  
P
Power Dissipation,  
per Package (Note 3.)  
500  
mW  
D
MC14538BCP  
MC14538BD  
2000/Box  
48/Rail  
T
A
Operating Temperature Range  
Storage Temperature Range  
–55 to +125  
–65 to +150  
260  
°C  
°C  
°C  
T
stg  
MC14538BDR2  
MC14538BDT  
SOIC–16 2500/Tape & Reel  
TSSOP–16 96/Rail  
T
Lead Temperature  
(8–Second Soldering)  
L
2. Maximum Ratings are those values beyond which damage to the device  
may occur.  
MC14538BDTR2 TSSOP–16 2500/Tape & Reel  
3. Temperature Derating:  
MC14538BDW  
SOIC–16  
47/Rail  
Plastic “P and D/DW” Packages: – 7.0 mW/ C From 65 C To 125 C  
MC14538BDWR2  
MC14538BF  
SOIC–16 1000/Tape & Reel  
This device contains protection circuitry to guard against damage due to high  
static voltages or electric fields. However, precautions must be taken to avoid  
applications of any voltage higher than maximum rated voltages to this  
SOEIAJ–16  
SOEIAJ–16  
See Note 1.  
See Note 1.  
MC14538BFEL  
high–impedancecircuit. For proper operation, V and V should be constrained  
in  
out  
to the range V  
(V or V  
)
V
.
SS  
in  
out  
DD  
1. For ordering information on the EIAJ version of  
the SOIC packages, please contact your local  
ON Semiconductor representative.  
Unused inputs must always be tied to an appropriate logic voltage level (e.g.,  
either V or V ). Unused outputs must be left open.  
SS  
DD  
Semiconductor Components Industries, LLC, 2000  
1
Publication Order Number:  
March, 2000 – Rev. 3  
MC14538B/D  
1234567...12

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