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MC14536BDWR2G PDF预览

MC14536BDWR2G

更新时间: 2024-01-09 13:24:34
品牌 Logo 应用领域
安森美 - ONSEMI 计时器或实时时钟微控制器和处理器外围集成电路光电二极管PC
页数 文件大小 规格书
14页 150K
描述
Programmable Timer

MC14536BDWR2G 技术参数

是否无铅:不含铅生命周期:Active
零件包装代码:SOIC包装说明:SOP,
针数:16Reach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
Factory Lead Time:1 week风险等级:0.54
Samacsys Confidence:3Samacsys Status:Released
Samacsys PartID:225196Samacsys Pin Count:16
Samacsys Part Category:Integrated CircuitSamacsys Package Category:Small Outline Packages
Samacsys Footprint Name:SOIC-16 WB CASE 751G-03 ISSUE DSamacsys Released Date:2015-08-07 09:42:55
Is Samacsys:N最大时钟频率:2 MHz
JESD-30 代码:R-PDSO-G16JESD-609代码:e3
长度:10.3 mm湿度敏感等级:3
端子数量:16计时器数量:1
最高工作温度:125 °C最低工作温度:-55 °C
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
峰值回流温度(摄氏度):260认证状态:Not Qualified
座面最大高度:2.65 mm最大供电电压:18 V
最小供电电压:3 V标称供电电压:5 V
表面贴装:YES技术:CMOS
温度等级:MILITARY端子面层:Tin (Sn)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:40
宽度:7.5 mmuPs/uCs/外围集成电路类型:TIMER, PROGRAMMABLE
Base Number Matches:1

MC14536BDWR2G 数据手册

 浏览型号MC14536BDWR2G的Datasheet PDF文件第7页浏览型号MC14536BDWR2G的Datasheet PDF文件第8页浏览型号MC14536BDWR2G的Datasheet PDF文件第9页浏览型号MC14536BDWR2G的Datasheet PDF文件第11页浏览型号MC14536BDWR2G的Datasheet PDF文件第12页浏览型号MC14536BDWR2G的Datasheet PDF文件第13页 
MC14536B  
+V  
16  
V
6
9
DD  
8−BYPASS  
R
4
5
X
A
OUT 1  
OUT 2  
10  
11  
12  
2
B
C
D
PULSE  
GEN.  
RESET  
SET  
1
7
CLOCK INH  
MONO−IN  
OSC INH  
15  
14  
3
13  
DECODE OUT  
IN  
CLOCK  
1
V
SS  
C
X
8
IN  
1
RESET  
*t .00247 R C 0.85  
w
X
X
t
R
C
in msec  
w
DECODE OUT  
in kW  
X
X
in pF  
*t  
w
POWERUP  
NOTE: When Power is first applied to the device with the RESET input going high, DECODE OUT initializes low. Bringing the RESET  
n
input low enables the chip’s internal counters. After RESET goes low, the 2 /2 negative transition of the clock input causes  
DECODE OUT to go high. Since the MONO−IN input is being used, the output becomes monostable. The pulse width of the  
n
output is dependent on the external timing components. The second and all subsequent pulses occur at 2 x (the clock period)  
intervals where n = the number of stages selected from the truth table.  
Figure 12. Time Interval Configuration Using an External Clock, Reset, and  
Output Monostable to Achieve a Pulse Output  
(Divide−by−4 Configured)  
http://onsemi.com  
10  

MC14536BDWR2G 替代型号

型号 品牌 替代类型 描述 数据表
CD4536BDW TI

功能相似

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MC14536BDWG ONSEMI

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完全替代

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