Order this document
by MC145192/D
SEMICONDUCTOR TECHNICAL DATA
Includes On–Board 64/65 Prescaler
F SUFFIX
SOG PACKAGE
CASE 751J
The MC145192 is a low–voltage single–package synthesizer with serial
interface capable of direct usage up to 1.1 GHz. A special architecture makes
this PLL very easy to program because a byte–oriented format is utilized. Due
to the patented BitGrabber registers, no address/steering bits are required for
random access of the three registers. Thus, tuning can be accomplished via a
3–byte serial transfer to the 24–bit A register. The interface is both SPI and
MICROWIRE compatible.
20
1
DT SUFFIX
TSSOP
CASE 948D
20
The device features a single–ended current source/sink phase detector A
output and a double–ended phase detector B output. Both phase detectors
have linear transfer functions (no dead zones). The maximum current of the
single–ended phase detector output is determined by an external resistor tied
from the Rx pin to ground. This current can be varied via the serial port.
1
ORDERING INFORMATION
MC145192F
MC145192DT TSSOP
SOG Package
The MC145192 phase/frequency detector B φ and φ outputs can be
R
V
powered from 2.7 to 5.5 V. This is optimized for 3.0 V systems. The
phase/frequency detector A PD output must be powered from 4.5 to 5.5 V,
out
and is optimized for a 5 volt supply.
PIN ASSIGNMENT
This part includes a differential RF input which may be operated in a
single–ended mode. Also featured are on–board support of an external crystal
and a programmable reference output. The R, A, and N counters are fully
programmable. The C register (configuration register) allows the part to be
configured to meet various applications. A patented feature allows the C
register to shut off unused outputs, thereby minimizing system noise and
interference.
In order to have consistent lock times and prevent erroneous data from being
loaded into the counters, on–board circuitry synchronizes the update of the A
register if the A or N counters are loading. Similarly, an update of the R register
is synchronized if the R counter is loading.
REF
1
2
3
4
5
6
20
19
18
17
16
15
REF
in
out
LD
DATA IN
φ
R
CLOCK
φ
V
ENABLE
OUTPUT A
OUTPUT B
V
PD
PD
out
GND
Rx
V
7
14
13
12
11
DD
8
TEST 2
The double–buffered R register allows new divide ratios to be presented to
the three counters (R, A, and N) simultaneously.
TEST 1
9
V
f
CC
•
•
•
•
Maximum Operating Frequency: 1100 MHz @ V = 200 mV p–p
in
10
f
in
in
Operating Supply Current: 6 mA Nominal at 2.7 V
Operating Supply Voltage Range (V
and V
Pins): 2.7 to 5.0 V
DD
Operating Supply Voltage Range of Phase Frequency Detector A
(V Pin) = 4.5 to 5.5 V
CC
PD
Operating Supply Voltage Range of Phase Detector B (V
•
•
•
•
•
•
•
•
•
•
•
Pin) = 2.7 to 5.5 V
PD
Current Source/Sink Phase Detector Output Capability: 2 mA Maximum
Gain of Current Source/Sink Phase/Frequency Detector Controllable via Serial Port
Operating Temperature Range: – 40° to 85°C
R Counter Division Range: (1 and) 5 to 8191
N Counter Division Range: 5 to 4095
A Counter Division Range: 0 to 63
Dual–Modulus Capability Provides Total Division up to 262,143
High–Speed Serial Interface: 2 Megabits per Second
Output A Pin, When Configured as Data Out, Permits Cascading of Devices
Two General–Purpose Digital Outputs — Output A: Totem–Pole (Push–Pull) with Four Output Modes
Output B: Open–Drain
•
Power–Saving Standby Feature with Patented Orderly Recovery for Minimizing Lock Times,
Standby Current: 30 µA
•
•
Evaluation Kit Available (Part Number MC145192EVK)
See Application Note AN1253/D for Low–Pass Filter Design, and
AN1277/D for Offset Reference PLLs for Fine Resolution or Fast Hopping
BitGrabber is a trademark of Motorola Inc. MICROWIRE is a trademark of National Semiconductor Corp.
REV 3
1/98
TN98012200
Motorola, Inc. 1998
MOTOROLA
MC145192
1
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