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MC145193/D PDF预览

MC145193/D

更新时间: 2024-10-02 14:43:27
品牌 Logo 应用领域
恩智浦 - NXP /
页数 文件大小 规格书
24页 462K
描述
PLL Frequency Synthesizer

MC145193/D 技术参数

生命周期:ActiveReach Compliance Code:unknown
风险等级:5.71Is Samacsys:N
模拟集成电路 - 其他类型:PLL FREQUENCY SYNTHESIZERBase Number Matches:1

MC145193/D 数据手册

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Freescale Semiconductor, Inc.  
Order this document by MC145193/D  
The MC145193 is recommended for new designs and offers reduced  
power consumption. The counters are programmed via a synchronous serial  
port which is SPI compatible. The serial port is byte-oriented to facilitate  
control via an MCU. Due to the innovative BitGrabber Plus registers, the  
MC145193 may be cascaded with other peripherals featuring BitGrabber  
Plus without requiring leading dummy bits or address bits in the serial data  
stream. In addition, BitGrabber Plus peripherals may be cascaded with  
existing BitGrabber peripherals.  
PLL FREQUENCY  
SYNTHESIZER  
SEMICONDUCTOR  
TECHNICAL DATA  
The device features a single–ended current source/sink phase detector A  
output and a double–ended phase detector B output. Both phase detectors  
have linear transfer functions (no dead zones). The maximum current of the  
single–ended phase detector output is determined by an external resistor  
tied from the Rx pin to ground. This current can be varied via the serial port.  
Slew–rate control is provided by a special driver designed for the REF  
out  
pin. This minimizes interference caused by REF  
.
out  
20  
This part includes a differential RF input that may be operated in a  
single–ended mode. Also featured are on–board support of an external  
crystal and a programmable reference output. The R, A, and N counters are  
fully programmable. The C register (configuration register) allows the part to  
be configured to meet various applications. A patented feature allows the C  
register to shut off unused outputs, thereby minimizing system noise and  
interference.  
In order to have consistent lock times and prevent erroneous data from  
being loaded into the counters, on–board circuitry synchronizes the update  
of the A register if the A or N counters are loading. Similarly, an update of the  
R register is synchronized if the R counter is loading.  
1
F SUFFIX  
PLASTIC PACKAGE  
CASE 751J  
(SO–20)  
The double–buffered R register allows new divide ratios to be presented  
to the three counters (R, A, and N) simultaneously.  
PIN CONNECTIONS  
Maximum Operating Frequency: 1100 MHz @ – 10 dBm  
Operating Supply Current: 3 mA Nominal at 3.0 V  
REF  
1
2
20  
19  
REF  
in  
out  
LD  
D
in  
Operating Supply Voltage Range (V , V , V  
Pins): 2.7 to 5.5 V  
φ
3
18 CLK  
17 ENB  
16  
DD CC PD  
R
Current Source/Sink Phase Detector Output:  
4
φ
V
V
PD  
1.7 mA @ 5.0 V or 1.0 mA @ 3.0 V  
5
Output A  
Gain of Current Source/Sink Phase/Frequency Detector Controllable via  
15  
14  
6
PD  
Output B  
out  
Gnd  
Rx  
Serial Port  
7
V
DD  
R Counter Division Range: 1 and 5 to 8191  
Dual–Modulus Capability Provides Total Division up to 262,143  
High–Speed Serial Interface: 4 Mbps  
8
13 Test 2  
9
12  
11  
V
CC  
Test 1  
f
in  
10  
f
in  
Output A Pin, When Configured as Data Out, Permits Cascading of  
(Top View)  
Devices  
Two General–Purpose Digital Outputs:  
Output A: Totem–Pole (Push–Pull) with Four Output Modes  
Output B: Open–Drain  
EVALUATION KIT  
Patented Power–Saving Standby Feature with Orderly Recovery for  
Minimizing Lock Times, Standby Current: 30 µA  
The MC145193EVK, which contains  
hardware and software, is available.  
See App Note AN1253/D for Low–Pass Filter Design, and AN1277/D for  
Offset Reference PLLs for Fine Resolution or Fast Hopping  
ORDERING INFORMATION  
Operating  
BitGrabber and BitGrabber Plus are trademarks of Motorola, Inc.  
Temperature Range  
Device  
Package  
MC145193F  
T
A
= –40 to 85°C  
SO–20  
Motorola, Inc. 2000  
Rev 1  
For More Information On This Product,  
Go to: www.freescale.com  

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