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MC145170P2

更新时间： 2024-01-28 17:56:27
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA /
页数 文件大小 规格书
27页 456K
描述
CMOS PLL FREQUENCY SYNTHESIZER WITH SERIAL INTERFACE

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MC145170P2 技术参数

生命周期：Transferred零件包装代码：DIP
包装说明：DIP,针数：16
Reach Compliance Code：unknownHTS代码：8542.39.00.01
风险等级：5.77模拟集成电路 - 其他类型：PLL FREQUENCY SYNTHESIZER
JESD-30 代码：R-PDIP-T16JESD-609代码：e0
长度：19.175 mm功能数量：1
端子数量：16最高工作温度：85 °C
最低工作温度：-40 °C封装主体材料：PLASTIC/EPOXY
封装代码：DIP封装形状：RECTANGULAR
封装形式：IN-LINE认证状态：Not Qualified
座面最大高度：4.44 mm最大供电电压 (Vsup)：5.5 V
最小供电电压 (Vsup)：2.7 V标称供电电压 (Vsup)：4.5 V
表面贴装：NO技术：CMOS
温度等级：INDUSTRIAL端子面层：Tin/Lead (Sn/Pb)
端子形式：THROUGH-HOLE端子节距：2.54 mm
端子位置：DUAL宽度：7.62 mm

MC145170P2 数据手册

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Order this document  
by MC145170–1/D  
SEMICONDUCTOR TECHNICAL DATA  
Advance Information  
P SUFFIX  
PLASTIC DIP  
CASE 648  
16  
16  
CMOS  
1
The new MC145170–1 is pin–for–pin compatible with the MC145170. A  
comparison of the two parts is shown in the table below. The MC145170–1 is  
recommended for new designs.  
D SUFFIX  
SOG PACKAGE  
CASE 751B  
1
The MC145170–1 is a single–chip synthesizer capable of direct usage in the  
MF, HF, and VHF bands. A special architecture makes this PLL the easiest to  
program in the industry. Either a bit– or byte–oriented format may be used. Due  
to the patented BitGrabber registers, no address/steering bits are required for  
random access of the three registers. Thus, tuning can be accomplished via a  
2–byte serial transfer to the 16–bit N register.  
DT SUFFIX  
TSSOP  
CASE 948C  
16  
1
ORDERING INFORMATION  
The device features fully programmable R and N counters, an amplifier at the  
f
pin, on–chip support of an external crystal, a programmable reference  
in  
MC145170P1 Plastic DIP  
MC145170D1 SOG Package  
MC145170DT1 TSSOP  
output, and both single– and double–ended phase detectors with linear transfer  
functions (no dead zones). A configuration (C) register allows the part to be  
configured to meet various applications. A patented feature allows the C  
register to shut off unused outputs, thereby minimizing noise and interference.  
In order to reduce lock times and prevent erroneous data from being loaded  
into the counters, a patented jam–load feature is included. Whenever a new  
divide ratio is loaded into the N register, both the N and R counters are  
jam–loaded with their respective values and begin counting down together. The  
phase detectors are also initialized during the jam load.  
PIN ASSIGNMENT  
OSC  
in  
1
2
3
4
5
6
16  
15  
14  
V
DD  
OSC  
REF  
φ
V
out  
out  
•
•
Operating Voltage Range: 2.5 to 5.5 V  
Maximum Operating Frequency:  
φ
R
f
in  
in  
PD  
185 MHz @ V = 500 mV p–p, 4.5 V Minimum Supply  
13  
12  
out  
in  
100 MHz @ V = 500 mV p–p, 3.0 V Minimum Supply  
in  
D
V
SS  
•
Operating Supply Current: 0.6 mA @ 3 V, 30 MHz  
1.5 mA @ 3 V, 100 MHz  
ENB  
CLK  
11  
LD  
3.0 mA @ 5 V, 50 MHz  
5.8 mA @ 5 V, 185 MHz  
f
7
8
10  
9
V
D
f
out  
R
•
•
•
•
Operating Temperature Range: – 40 to 85°C  
R Counter Division Range: 1 and 5 to 32,767  
N Counter Division Range: 40 to 65,535  
Direct Interface to Motorola SPI and National MICROWIRE Serial Data  
Ports  
•
•
Chip Complexity: 4800 FETs or 1200 Equivalent Gates  
See Application Note AN1207/D  
COMPARISION OF THE PLL FREQUENCY SYNTHESIZERS  
Parameter  
MC145170–1  
1.2 µm CMOS  
185 MHz  
25 MHz  
MC145170  
1.5 µm CMOS  
160 MHz  
20 MHz  
Technology  
Maximum Frequency with 5 V ± 10% Supply, f  
in  
Maximum Frequency with 5 V ± 10% Supply, OSC  
in  
Maximum Supply Voltage  
5.5 V  
6.0 V  
Maximum Input Capacitance, f  
in  
7 pF  
5 pF  
This document contains information on a new product. Specifications and information herein are subject to change without notice.  
BitGrabber is a trademark of Motorola Inc. MICROWIRE is a trademark of National Semiconductor Corp.  
REV 1  
3/96  
Motorola, Inc. 1996  
1234567...27

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