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MC14517BCL

更新时间： 2024-02-10 15:28:34
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 移位寄存器触发器逻辑集成电路输出元件
页数 文件大小 规格书
6页 212K
描述
Dual 64-Bit Static Shift Register

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中文翻译

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MC14517BCL 技术参数

是否无铅：不含铅生命周期：Active
零件包装代码：SOIC包装说明：SOP, SOP16,.4
针数：16Reach Compliance Code：compliant
HTS代码：8542.39.00.01Factory Lead Time：1 week
风险等级：1.01Is Samacsys：N
其他特性：16-BIT, 32-BIT AND 48-BIT OUTPUT ALSO AVAILABLE计数方向：RIGHT
系列：4000/14000/40000JESD-30 代码：R-PDSO-G16
JESD-609代码：e3长度：10.3 mm
逻辑集成电路类型：SERIAL IN SERIAL OUT最大频率@ Nom-Sup：1500000 Hz
湿度敏感等级：3位数：64
功能数量：2端子数量：16
最高工作温度：125 °C最低工作温度：-55 °C
输出特性：3-STATE输出极性：TRUE
封装主体材料：PLASTIC/EPOXY封装代码：SOP
封装等效代码：SOP16,.4封装形状：RECTANGULAR
封装形式：SMALL OUTLINE峰值回流温度（摄氏度）：260
电源：5/15 V传播延迟（tpd）：770 ns
认证状态：Not Qualified座面最大高度：2.65 mm
子类别：Shift Registers最大供电电压 (Vsup)：18 V
最小供电电压 (Vsup)：3 V标称供电电压 (Vsup)：5 V
表面贴装：YES技术：CMOS
温度等级：MILITARY端子面层：Tin (Sn)
端子形式：GULL WING端子节距：1.27 mm
端子位置：DUAL处于峰值回流温度下的最长时间：40
触发器类型：POSITIVE EDGE宽度：7.5 mm
最小 fmax：5.3 MHzBase Number Matches：1

MC14517BCL 数据手册

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SEMICONDUCTOR TECHNICAL DATA  
The MC14517B dual 64–bit static shift register consists of two identical,  
independent, 64–bit registers. Each register has separate clock and write  
enable inputs, as well as outputs at bits 16, 32, 48, and 64. Data at the data  
input is entered by clocking, regardless of the state of the write enable input.  
An output is disabled (open circuited) when the write enable input is high.  
During this time, data appearing at the data input as well as the 16–bit,  
32–bit, and 48–bit taps may be entered into the device by application of a  
clock pulse. This feature permits the register to be loaded with 64 bits in 16  
clock periods, and also permits bus logic to be used. This device is useful in  
time delay circuits, temporary memory storage circuits, and other serial shift  
register applications.  
L SUFFIX  
CERAMIC  
CASE 620  
P SUFFIX  
PLASTIC  
CASE 648  
•
•
•
•
Diode Protection on All Inputs  
Fully Static Operation  
Output Transitions Occur on the Rising Edge of the Clock Pulse  
Exceedingly Slow Input Transition Rates May Be Applied to the Clock  
Input  
3–State Output at 64th–Bit Allows Use in Bus Logic Applications  
Shift Registers of any Length may be Fully Loaded with 16 Clock Pulses  
Supply Voltage Range = 3.0 Vdc to 18 Vdc  
Capable of Driving Two Low–power TTL Loads or One Low–power  
Schottky TTL Load Over the Rated Temperature Range  
DW SUFFIX  
SOIC  
CASE 751G  
ORDERING INFORMATION  
MC14XXXBCP  
MC14XXXBCL  
MC14XXXBDW  
Plastic  
Ceramic  
SOIC  
•
•
•
•
T
A
= – 55° to 125°C for all packages.  
MAXIMUM RATINGS (Voltages referenced to V  
)
SS  
PIN ASSIGNMENT  
Symbol  
Parameter  
DC Supply Voltage  
Input or Output Voltage (DC or Transient)  
Value  
Unit  
V
Q16  
Q48  
WE  
C
1
2
16  
15  
V
A
A
A
A
A
A
DD  
Q16  
V
DD  
– 0.5 to + 18.0  
B
V , V  
– 0.5 to V  
DD  
+ 0.5  
V
in out  
I , I  
3
4
5
6
7
8
14  
13  
12  
11  
10  
9
Q48  
WE  
Input or Output Current (DC or Transient),  
per Pin  
± 10  
mA  
B
in out  
B
P
Power Dissipation, per Package†  
Storage Temperature  
500  
mW  
C
D
Q64  
Q32  
C
B
T
stg  
– 65 to + 150  
260  
Q64  
B
B
T
L
Lead Temperature (8–Second Soldering)  
C
D
Q32  
A
* Maximum Ratings are those values beyond which damage to the device may occur.  
†Temperature Derating:  
V
D
B
SS  
Plastic “P and D/DW” Packages: – 7.0 mW/ C From 65 C To 125 C  
Ceramic “L” Packages: – 12 mW/ C From 100 C To 125 C  
FUNCTIONAL TRUTH TABLE (X = Don’t Care)  
Write  
Clock Enable  
Data  
16–Bit Tap  
32–Bit Tap  
48–Bit Tap  
64–Bit Tap  
0
0
X
Content of 16–Bit  
Displayed  
Content of 32–Bit  
Displayed  
Content of 48–Bit  
Displayed  
Content of 64–Bit  
Displayed  
0
1
1
0
X
X
High Impedance  
High Impedance  
High Impedance  
High Impedance  
Content of 16–Bit  
Displayed  
Content of 32–Bit  
Displayed  
Content of 48–Bit  
Displayed  
Content of 64–Bit  
Displayed  
1
1
0
X
High Impedance  
High Impedance  
High Impedance  
High Impedance  
Data entered  
into 1st Bit  
Content of 16–Bit  
Displayed  
Content of 32–Bit  
Displayed  
Content of 48–Bit  
Displayed  
Content of 64–Bit  
Displayed  
1
0
1
Data entered  
into 1st Bit  
Data at tap  
Data at tap  
Data at tap  
High Impedance  
entered into 17–Bit entered into 33–Bit entered into 49–Bit  
X
Content of 16–Bit  
Displayed  
Content of 32–Bit  
Displayed  
Content of 48–Bit  
Displayed  
Content of 64–Bit  
Displayed  
X
High Impedance  
High Impedance  
High Impedance  
High Impedance  
REV 3  
1/94  
Motorola, Inc. 1995  
123456

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