Datasheet > MC145181FTAR2

MC145181FTAR2

更新时间： 2024-02-18 13:49:38

品牌	Logo	应用领域
飞思卡尔 - FREESCALE		信息通信管理
页数	文件大小	规格书
71页	957K
描述
Dual 550/60 MHz PLL Frequency Synthesizer with DACs and Voltage Multiplier

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MC145181FTAR2 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
包装说明：	PLASTIC, LQFP-32	Reach Compliance Code：	unknown
HTS代码：	8542.39.00.01	风险等级：	5.73
模拟集成电路 - 其他类型：	PLL FREQUENCY SYNTHESIZER	JESD-30 代码：	S-PQFP-G32
JESD-609代码：	e0	长度：	5 mm
功能数量：	1	端子数量：	32
最高工作温度：	85 °C	最低工作温度：	-40 °C
封装主体材料：	PLASTIC/EPOXY	封装代码：	LFQFP
封装等效代码：	QFP32,.28SQ,20	封装形状：	SQUARE
封装形式：	FLATPACK, LOW PROFILE, FINE PITCH	峰值回流温度（摄氏度）：	NOT SPECIFIED
电源：	2/3.3 V	认证状态：	Not Qualified
座面最大高度：	1.6 mm	子类别：	PLL or Frequency Synthesis Circuits
最大供电电压 (Vsup)：	3.6 V	最小供电电压 (Vsup)：	1.8 V
表面贴装：	YES	技术：	BICMOS
温度等级：	INDUSTRIAL	端子面层：	Tin/Lead (Sn/Pb)
端子形式：	GULL WING	端子节距：	0.5 mm
端子位置：	QUAD	处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	5 mm	Base Number Matches：	1

MC145181FTAR2 数据手册

Freescale Semiconductor, Inc_O._{rder this document by MC145181/D}

BiCMOS COMPONENT

FOR 2 OR 3 VOLT

The MC145181 is a dual frequency synthesizer containing very–low

supply voltage circuitry. The device supports two independent loops with a

single input reference and operates down to 1.8 V. Phase noise reduction

circuitry is incorporated into the device.

The MC145181 operates up to 550 MHz on the main loop and up to

60 MHz on the secondary loop. The device has a 32/33 prescaler for the

main loop. Lock detection circuitry for both loops is multiplexed to a single

output.

SYSTEMS

SEMICONDUCTOR

TECHNICAL DATA

Two 8–bit DACs are powered through a dedicated pin. The DAC supply

range is 1.8 to 3.6 V; this voltage may differ from the main supply.

An on–chip voltage multiplier supplies power to the phase/frequency

detectors. Thus, in a 2 V application, the detectors are supplied with 4 V

power. In 2.6 to 3.6 V applications, the multiplied voltage is regulated at

approximately 5 V. The current source/sink phase/frequency detector for the

main loop is designed to achieve faster lock times than a conventional

detector. Both high and low current outputs are available along with a timer,

double buffers, and a MOSFET switch to adjust the external low–pass filter

response.

There are several levels of standby which are controllable with a 1–byte

transfer through the serial port. Either of the PLLs and/or the reference

oscillator may be independently placed in the low–power standby state. In

addition, any of the phase/frequency detector outputs may be placed in the

floating state to facilitate modulation of the external VCOs. Either DAC may

be placed in standby via a 4–byte transfer.

(Scale 2:1)

PLASTIC PACKAGE

CASE 873C

(LQFP–32, Tape & Reel Only)

VERY–SMALL 5 x 5 mm BODY

DEVELOPMENT SYSTEM

The MC145230EVK, which contains hardware and

software, is strongly recommended for system

development. (The user must provide the VCOs for

evaluating the MC145181.) The software supports

all features and modes of operation of the device. Up

to four boards or devices can be controlled and the

user is alerted to error conditions. The control

program may be used with any board based on the

MC145181, MC145225, or MC145230.

The MC145181 facilitates designing the receiver’s first and second local

oscillators for ReFLEX two–way paging applications. Also, the device

accommodates generation of the transmit carrier.

• Operating Frequency

Main Loop: 100 to 550 MHz

Secondary Loop: 10 to 60 MHz

• Operating Supply Voltage: 1.8 to 3.6 V

• Nominal Supply Current, Both Loops Active: 3 mA

• Maximum Standby Current, All Systems Shut Down: 10 µA

• Phase Detector Output Current:

ORDERING INFORMATION

1.8 V Supply — PD –Hi: 2.8 mA, PD –Lo: 0.7 mA

out out

2.5 V Supply — PD –Hi: 4.4 mA, PD –Lo: 1.1 mA

out out

Main/Secondary

Loop

Maximum

Frequency

• Two Independent 8–Bit DACs with Separate Supply Pin (Up to 3.6 V)

• Lock Detect Output with Adjustable Lock Indication Window

• Independent R Counters Allow Independent Step Sizes for Each Loop

• Main Loop Divider Range: 992 to 262,143

Device

Package

MC145181FTAR2

550/60 MHz

LQFP–32

• Secondary Loop Divider Range: 7 to 8,191

• Fractional Reference Counters Divider Range: 20 to 32,767.5

• Auxiliary Reference Divider with Small–Signal Differential

Output — Ratios: 8, 10, 12.5

• Three General–Purpose Outputs

• Direct Interface to Motorola SPI Data Port Up to 10 Mbps

ReFLEX and BitGrabber are trademarks of Motorola, Inc.

This document contains information on a new product. Specifications and information herein

are subject to change without notice.

Motorola, Inc. 1999

Rev 1

MOTOROLA RF/IF DEVICE DATA

For More Information On This Product,

Go to: www.freescale.com

12 3 4 5 6 7...71

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MC14518BCPD	MOTOROLA	获取价格	4000/14000/40000 SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT UP DECADE COUNTER, PDIP16
MC14518BCPDS	MOTOROLA	获取价格	4000/14000/40000 SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT UP DECADE COUNTER, PDIP16, PLAS

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