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MC14515BDWR2G PDF预览

MC14515BDWR2G

更新时间: 2024-11-03 05:10:19
品牌 Logo 应用领域
安森美 - ONSEMI 锁存器
页数 文件大小 规格书
8页 114K
描述
4−Bit Transparent Latch / 4−to−16 Line Decoder

MC14515BDWR2G 技术参数

是否无铅: 不含铅生命周期:Active
零件包装代码:SOIC包装说明:SOP, SOP24,.4
针数:24Reach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
Factory Lead Time:25 weeks风险等级:1.57
其他特性:ADDRESS LATCHES系列:4000/14000/40000
输入调节:LATCHEDJESD-30 代码:R-PDSO-G24
JESD-609代码:e3长度:15.395 mm
负载电容(CL):50 pF逻辑集成电路类型:OTHER DECODER/DRIVER
最大I(ol):0.00064 A湿度敏感等级:3
功能数量:1端子数量:24
最高工作温度:125 °C最低工作温度:-55 °C
输出极性:INVERTED封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP24,.4
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
包装方法:RAIL峰值回流温度(摄氏度):250
电源:5/15 VProp。Delay @ Nom-Sup:1100 ns
传播延迟(tpd):1100 ns认证状态:Not Qualified
座面最大高度:2.65 mm子类别:Decoder/Drivers
最大供电电压 (Vsup):18 V最小供电电压 (Vsup):3 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:MILITARY
端子面层:Tin (Sn)端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:40宽度:7.5 mm
Base Number Matches:1

MC14515BDWR2G 数据手册

 浏览型号MC14515BDWR2G的Datasheet PDF文件第2页浏览型号MC14515BDWR2G的Datasheet PDF文件第3页浏览型号MC14515BDWR2G的Datasheet PDF文件第4页浏览型号MC14515BDWR2G的Datasheet PDF文件第5页浏览型号MC14515BDWR2G的Datasheet PDF文件第6页浏览型号MC14515BDWR2G的Datasheet PDF文件第7页 
MC14514B, MC14515B  
4−Bit Transparent Latch /  
4−to−16 Line Decoder  
The MC14514B and MC14515B are two output options of a 4 to 16  
line decoder with latched inputs. The MC14514B (output active high  
option) presents a logical “1” at the selected output, whereas the  
MC14515B (output active low option) presents a logical “0” at the  
selected output. The latches are R−S type flip−flops which hold the  
last input data presented prior to the strobe transition from “1” to “0”.  
These high and low options of a 4−bit latch / 4 to 16 line decoder are  
constructed with N−channel and P−channel enhancement mode  
devices in a single monolithic structure. The latches are R−S type  
flip−flops and data is admitted upon a signal incident at the strobe  
input, decoded, and presented at the output.  
http://onsemi.com  
MARKING  
DIAGRAMS  
24  
1
PDIP−24  
P SUFFIX  
CASE 709  
1
MC145xxBCP  
AWLYYWWG  
These complementary circuits find primary use in decoding  
applications where low power dissipation and/or high noise immunity  
is desired.  
Features  
Supply Voltage Range = 3.0 Vdc to 18 Vdc  
24  
1
SOIC−24  
DW SUFFIX  
CASE 751E  
MC145xxB  
AWLYYWWG  
Capable of Driving Two Low−power TTL Loads or One Low−power  
Schottky TTL Load the Rated Temperature Range  
Pb−Free Packages are Available*  
1
xx  
A
= 14 or 15  
= Assembly Location  
MAXIMUM RATINGS (Voltages Referenced to V  
)
SS  
WL = Wafer Lot  
YY = Year  
WW = Work Week  
= Pb−Free Package  
Parameter  
Symbol  
Value  
Unit  
V
DC Supply Voltage Range  
V
DD  
0.5 to +18.0  
G
Input or Output Voltage Range  
(DC or Transient)  
V , V  
in out  
0.5 to V  
+0.5  
V
DD  
Input or Output Current (DC or Transient) I , I  
per Pin  
10  
mA  
in out  
PIN ASSIGNMENT  
Power Dissipation per Package (Note 1)  
Ambient Temperature Range  
Storage Temperature Range  
Lead Temperature (8−Second Soldering)  
P
500  
mW  
°C  
D
ST  
D1  
D2  
S7  
S6  
S5  
1
2
3
4
5
6
24  
V
DD  
T
A
55 to +125  
65 to +150  
260  
23 INH  
22 D4  
21 D3  
20 S10  
19 S11  
T
stg  
°C  
T
°C  
L
Stresses exceeding Maximum Ratings may damage the device. Maximum  
Ratings are stress ratings only. Functional operation above the Recommended  
Operating Conditions is not implied. Extended exposure to stresses above the  
Recommended Operating Conditions may affect device reliability.  
1. Temperature Derating: Plastic “P and D/DW”  
S4  
S3  
S1  
7
8
9
18 S8  
17 S9  
16 S14  
15 S15  
14 S12  
13 S13  
Packages: – 7.0 mW/_C From 65_C To 125_C  
This device contains protection circuitry to guard against damage due to high  
static voltages or electric fields. However, precautions must be taken to avoid  
applications of any voltage higher than maximum rated voltages to this  
S2 10  
S0 11  
high−impedance circuit. For proper operation, V and V should be constrained  
in  
out  
to the range V v (V or V ) v V  
.
SS  
in  
out  
DD  
Unused inputs must always be tied to an appropriate logic voltage level  
V
SS  
12  
(e.g., either V or V ). Unused outputs must be left open.  
SS  
DD  
ORDERING INFORMATION  
*For additional information on our Pb−Free strategy and soldering details, please  
download the ON Semiconductor Soldering and Mounting Techniques  
Reference Manual, SOLDERRM/D.  
See detailed ordering and shipping information in the package  
dimensions section on page 2 of this data sheet.  
© Semiconductor Components Industries, LLC, 2006  
1
Publication Order Number:  
June, 2006 − Rev. 6  
MC14514B/D  
 

MC14515BDWR2G 替代型号

型号 品牌 替代类型 描述 数据表
CD4515BM TI

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CD74ACT138E TI

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