ML145162
60 MHz and 85 MHz Universal
Programmable Dual PLL Frequency
Synthesizers
CMOS
Legacy Device: Motorola MC145162
The ML145162 is a dual phase–locked loop (PLL) frequency synthesizer
especially designed for CT–1 cordless phone applications worldwide. This
frequency synthesizer is also for any product with a frequency operation at
60MHz or below.
P DIP 16 = EP
PLASTIC DIP
CASE 648
16
1
The device features fully programmable receive, transmit, reference, and
auxiliary reference counters accessed through an MCU serial interface. This
feature allows this device to operate in any CT–1 cordless phone application.
The device consists of two independent phase detectors for transmit and
receive loops. A common reference oscillator, driving two independent refer-
ence frequency counters, provides independent reference frequencies for
transmit and receive loops. The auxiliary reference counter allows the user to
select an additional reference frequency for receive and transmit loops if
required.
SOG 16 = -5P
SOG PACKAGE
CASE 751B
16
1
CROSS REFERENCE/ORDERING INFORMATION
PACKAGE
MOTOROLA
LANSDALE
P DIP 16
SOG 16
MC145162P
MC145162D
ML145162EP
ML145162-5P
• Operating Voltage Range: 2.5 to 5.5 V
Note: Lansdale lead free (Pb) product, as it
becomes available, will be identified by a part
number prefix change from ML to MLE.
• Operating Temperature Range: T = – 40 to +75°C
A
• Operating Power Consumption: 3.0 mA @ 2.5 V
• Maximum Operating Frequency: 60 MHz @ 200 mV p–p, V
• Three or Four Pins Used for Serial MCU Interface
= 2.5 V
DD
• Built–In MCU Clock Output with Frequency of Reference Oscillator ÷3/÷4
• Power Saving Mode Controlled by MCU
• Lock Detect Signal
• On–Chip Reference Oscillator Supports External Crystals to 16.0 MHz
• Reference Frequency Counter Division Range: 16 to 4095
• Auxiliary Reference Frequency Counter Division Range: 16 to 16,383
• Transmit Counter Division Range: 16 to 65,535
PIN ASSIGNMENT
CLK
1
2
16
15
LD
AD
in
TxPD
out
D
3
4
5
6
7
8
14
13
12
11
10
9
f
–T
in
in
ENB
TxPS/f
Tx
• Receive Counter Division Range: 16 to 65,535
MCUCLK
V
DD
RxPS/F
V
SS
Rx
OSC
in
RxPD
out
OSC
out
f
–R
in
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