The MC14514B and MC14515B are two output options of a 4 to 16
line decoder with latched inputs. The MC14514B (output active high
option) presents a logical “1” at the selected output, whereas the
MC14515B (output active low option) presents a logical “0” at the
selected output. The latches are R–S type flip–flops which hold the
last input data presented prior to the strobe transition from “1” to “0”.
These high and low options of a 4–bit latch/4 to 16 line decoder are
constructed with N–channel and P–channel enhancement mode
devices in a single monolithic structure. The latches are R–S type
flip–flops and data is admitted upon a signal incident at the strobe
input, decoded, and presented at the output.
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MARKING
DIAGRAMS
24
PDIP–24
P SUFFIX
CASE 709
These complementary circuits find primary use in decoding
applications where low power dissipation and/or high noise immunity
is desired.
MC145XXBCP
AWLYYWW
• Supply Voltage Range = 3.0 Vdc to 18 Vdc
1
• Capable of Driving Two Low–power TTL Loads or One Low–power
Schottky TTL Load Over the Rated Temperature Range
24
MAXIMUM RATINGS (Voltages Referenced to V ) (Note 1.)
SS
Symbol
Parameter
Value
Unit
V
SOIC–24
DW SUFFIX
CASE 751E
145XXB
AWLYYWW
V
DD
DC Supply Voltage Range
–0.5 to +18.0
V , V
in out
Input or Output Voltage Range
(DC or Transient)
–0.5 to V + 0.5
V
DD
1
I , I
in out
Input or Output Current
(DC or Transient) per Pin
±10
mA
XX
A
= Specific Device Code
= Assembly Location
P
D
Power Dissipation,
500
mW
WL or L = Wafer Lot
per Package (Note 2.)
YY or Y = Year
WW or W = Work Week
T
Ambient Temperature Range
Storage Temperature Range
–55 to +125
–65 to +150
260
°C
°C
°C
A
T
stg
ORDERING INFORMATION
T
Lead Temperature
L
(8–Second Soldering)
Device
Package
PDIP–24
SOIC–24
Shipping
1. Maximum Ratings are those values beyond which damage to the device
may occur.
2. Temperature Derating:
MC14514BCP
MC14514BDW
MC14514BDWR2
15/Rail
30/Rail
Plastic “P and D/DW” Packages: – 7.0 mW/ C From 65 C To 125 C
SOIC–24 1000/Tape & Reel
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
MC14515BCP
MC14515BDW
MC14515BDWR2
PDIP–24
SOIC–24
15/Rail
30/Rail
high–impedancecircuit. For proper operation, V and V should be constrained
in
out
to the range V
(V or V
)
V
DD
.
SS
in
out
Unused inputs must always be tied to an appropriate logic voltage level (e.g.,
either V or V ). Unused outputs must be left open.
SOIC–24 1000/Tape & Reel
SS
DD
Semiconductor Components Industries, LLC, 2000
1
Publication Order Number:
March, 2000 – Rev. 3
MC14514B/D