SEMICONDUCTOR TECHNICAL DATA
The MC14514B and MC14515B are two output options of a 4 to 16 line
decoder with latched inputs. The MC14514B (output active high option)
presents a logical “1” at the selected output, whereas the MC14515B (output
active low option) presents a logical “0” at the selected output. The latches
are R–S type flip–flops which hold the last input data presented prior to the
strobe transition from “1” to “0”. These high and low options of a 4–bit latch/4
to 16 line decoder are constructed with N–channel and P–channel
enhancement mode devices in a single monolithic structure. The latches are
R–S type flip–flops and data is admitted upon a signal incident at the strobe
input, decoded, and presented at the output.
L SUFFIX
CERAMIC
CASE 623
P SUFFIX
PLASTIC
CASE 709
These complementary circuits find primary use in decoding applications
where low power dissipation and/or high noise immunity is desired.
DW SUFFIX
SOIC
CASE 751E
•
•
Supply Voltage Range = 3.0 Vdc to 18 Vdc
Capable of Driving Two Low–power TTL Loads or One Low–power
Schottky TTL Load Over the Rated Temperature Range
ORDERING INFORMATION
MC14XXXBCP
MC14XXXBCL
MC14XXXBDW
Plastic
Ceramic
SOIC
MAXIMUM RATINGS* (Voltages Referenced to V
)
SS
Symbol
Parameter
DC Supply Voltage
Value
Unit
V
T
A
= – 55° to 125°C for all packages.
V
DD
– 0.5 to + 18.0
V , V
Input or Output Voltage (DC or Transient)
0.5 to V
DD
+ 0.5
V
in out
I , I
Input or Output Current (DC or Transient),
per Pin
± 10
mA
in out
P
Power Dissipation, per Package†
Storage Temperature
500
mW
C
D
T
stg
– 65 to + 150
260
T
Lead Temperature (8–Second Soldering)
C
L
DECODE TRUTH TABLE (Strobe = 1)*
* Maximum Ratings are those values beyond which damage to the device may occur.
†Temperature Derating:
Selected Output
Data Inputs
MC14514 = Logic “1”
MC14515 = Logic “0”
Plastic “P and D/DW” Packages: – 7.0 mW/ C From 65 C To 125 C
Ceramic “L” Packages: – 12 mW/ C From 100 C To 125 C
Inhibit
D
C
B
A
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
1
S0
S1
S2
S3
BLOCK DIAGRAM
11
S0
A B C D
9
S1
S2
A B C D
A B C D
10
8
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
1
0
1
S4
S5
S6
S7
V
V
= PIN 24
= PIN 12
DD
SS
S3
S4
S5
A B C D
A B C D
A B C D
7
6
2
3
A
B
C
D
0
0
0
0
1
1
1
1
0
0
0
0
0
0
1
1
0
1
0
1
S8
S9
S10
S11
DATA 1
DATA 2
5
S6
S7
A B C D
A B C D
A B C D
A B C D
A B C D
A B C D
A B C D
A B C D
A B C D
4
TRANSPARENT
LATCH
4 TO 16
DECODER
18
17
20
19
14
13
16
15
21
22
S8
0
0
0
0
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
S12
S13
S14
S15
DATA 3
DATA 4
S9
S10
S11
S12
S13
S14
1
X
X
X
X
All Outputs = 0, MC14514
All Outputs = 1, MC14515
1
STROBE
X = Don’t Care
*Strobe = 0, Data is latched
S15
A B C D
23
INHIBIT
REV 3
1/94
Motorola, Inc. 1995
MOTOROLA CMOS LOGIC DATA
MC14514B MC14515B
385