MC14514B, MC14515B
4−Bit Transparent Latch /
4−to−16 Line Decoder
The MC14514B and MC14515B are two output options of a 4 to 16
line decoder with latched inputs. The MC14514B (output active high
option) presents a logical “1” at the selected output, whereas the
MC14515B (output active low option) presents a logical “0” at the
selected output. The latches are R−S type flip−flops which hold the
last input data presented prior to the strobe transition from “1” to “0”.
These high and low options of a 4−bit latch / 4 to 16 line decoder are
constructed with N−channel and P−channel enhancement mode
devices in a single monolithic structure. The latches are R−S type
flip−flops and data is admitted upon a signal incident at the strobe
input, decoded, and presented at the output.
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MARKING
DIAGRAMS
24
1
PDIP−24
P SUFFIX
CASE 709
1
MC145xxBCP
AWLYYWWG
These complementary circuits find primary use in decoding
applications where low power dissipation and/or high noise immunity
is desired.
Features
• Supply Voltage Range = 3.0 Vdc to 18 Vdc
24
1
SOIC−24
DW SUFFIX
CASE 751E
MC145xxB
AWLYYWWG
• Capable of Driving Two Low−power TTL Loads or One Low−power
Schottky TTL Load the Rated Temperature Range
• Pb−Free Packages are Available*
1
xx
A
= 14 or 15
= Assembly Location
MAXIMUM RATINGS (Voltages Referenced to V
)
SS
WL = Wafer Lot
YY = Year
WW = Work Week
= Pb−Free Package
Parameter
Symbol
Value
Unit
V
DC Supply Voltage Range
V
DD
−0.5 to +18.0
G
Input or Output Voltage Range
(DC or Transient)
V , V
in out
−0.5 to V
+0.5
V
DD
Input or Output Current (DC or Transient) I , I
per Pin
10
mA
in out
PIN ASSIGNMENT
Power Dissipation per Package (Note 1)
Ambient Temperature Range
Storage Temperature Range
Lead Temperature (8−Second Soldering)
P
500
mW
°C
D
ST
D1
D2
S7
S6
S5
1
2
3
4
5
6
24
V
DD
T
A
−55 to +125
−65 to +150
260
23 INH
22 D4
21 D3
20 S10
19 S11
T
stg
°C
T
°C
L
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. Temperature Derating: Plastic “P and D/DW”
S4
S3
S1
7
8
9
18 S8
17 S9
16 S14
15 S15
14 S12
13 S13
Packages: – 7.0 mW/_C From 65_C To 125_C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
S2 10
S0 11
high−impedance circuit. For proper operation, V and V should be constrained
in
out
to the range V v (V or V ) v V
.
SS
in
out
DD
Unused inputs must always be tied to an appropriate logic voltage level
V
SS
12
(e.g., either V or V ). Unused outputs must be left open.
SS
DD
ORDERING INFORMATION
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
© Semiconductor Components Industries, LLC, 2006
1
Publication Order Number:
June, 2006 − Rev. 6
MC14514B/D