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MC14032B PDF预览

MC14032B

更新时间: 2024-09-22 22:58:11
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA /
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7页 253K
描述
Triple Serial Adders

MC14032B 数据手册

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SEMICONDUCTOR TECHNICAL DATA  
The MC14032B and MC14038B triple serial adders have the clock and  
carry reset inputs common to all three adders. The carry is added on the  
positive–going clock transition for the MC14032B, and on the negative–  
going clock transition for the MC14038B. Typical applications include serial  
arithmetic units, digital correlators, digital servo control systems, datalink  
computers, and flight control computers.  
L SUFFIX  
CERAMIC  
CASE 620  
Buffered Outputs  
Single–Phase Clocking  
Supply Voltage Range = 3.0 Vdc to 18 Vdc  
Capable of Driving Two Low–power TTL Loads or One Low–power  
Schottky TTL Load Over the Rated Temperature Range.  
Pin–for–Pin Replacement for CD4032B and CD4038B.  
P SUFFIX  
PLASTIC  
CASE 648  
D SUFFIX  
SOIC  
CASE 751B  
MAXIMUM RATINGS* (Voltages Referenced to V  
)
SS  
ORDERING INFORMATION  
Symbol  
Parameter  
DC Supply Voltage  
Value  
Unit  
V
MC14XXXBCP  
MC14XXXBCL  
MC14XXXBD  
Plastic  
Ceramic  
SOIC  
V
DD  
– 0.5 to + 18.0  
V , V  
Input or Output Voltage (DC or Transient)  
– 0.5 to V  
DD  
+ 0.5  
V
in out  
l , l  
T
= – 55° to 125°C for all packages.  
A
Input or Output Current (DC or Transient),  
per Pin  
± 10  
mA  
in out  
P
Power Dissipation, per Package†  
Storage Temperature  
500  
mW  
C
D
BLOCK DIAGRAM  
T
stg  
– 65 to + 150  
260  
A1 10  
B1 11  
T
Lead Temperature (8–Second Soldering)  
C
L
ADDER 1  
ADDER 2  
ADDER 3  
9 S1  
INVERT 1  
7
* Maximum Ratings are those values beyond which damage to the device may occur.  
Temperature Derating:  
Plastic “P and D/DW” Packages: – 7.0 mW/ C From 65 C To 125 C  
Ceramic “L” Packages: – 12 mW/ C From 100 C To 125 C  
A2 13  
B2 12  
INVERT 2  
4 S2  
5
This device contains protection circuitry to guard against damage  
due to high static voltages or electric fields. However, precautions must  
be taken to avoid applications of any voltage higher than maximum rated  
V
V
= PIN 16  
DD  
= PIN 8  
SS  
voltages to this high-impedance circuit. For proper operation, V and  
A3 15  
B3 14  
INVERT 3  
in  
V
out  
should be constrained to the range V  
SS  
(V or V ) V .  
in out DD  
1 S3  
Unused inputs must always be tied to an appropriate logic voltage  
level (e.g., either V or V ). Unused outputs must be left open.  
2
3
6
CLOCK  
SS DD  
CARRY RESET  
LOGIC DIAGRAMS  
(ONE SECTION AND COMMON INPUTS SHOWN)  
MC14032B  
MC14038B  
A
B
A
B
S
S
D
C
Q
D
C
Q
R
R
INVERT  
INVERT  
CARRY  
RESET  
CARRY  
RESET  
D
Q
D
C
Q
C
TO  
TO  
NEXT  
STAGE  
NEXT  
STAGE  
CLOCK  
CLOCK  
REV 3  
1/94  
Motorola, Inc. 1995  

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