SEMICONDUCTOR TECHNICAL DATA
L SUFFIX
CERAMIC
CASE 623
The MC14034B is a bidirectional 8–bit static parallel/serial, input/output
bus register. The device contains two sets of input/output lines which allows
the bidirectional transfer of data between two buses; the conversion of serial
data to parallel form, or the conversion of parallel data to serial form.
Additionally the serial data input allows data to be entered shift/right, while
shift/left can be accomplished by hard–wiring each parallel output to the
previous parallel bit input.
Other useful applications for this device include pseudo–random code
generation, sample and hold register, frequency and phase–comparator,
address or buffer register, and serial/parallel input/output conversions.
P SUFFIX
PLASTIC
CASE 709
DW SUFFIX
SOIC
CASE 751E
•
•
•
•
Bidirectional Parallel Data Input
Diode Protection on All Inputs
Supply Voltage Range = 3.0 Vdc to 18 Vdc
Capable of Driving Two Low–power TTL Loads or One Low–power
Schottky TTL Load Over the Rated Temperature Range.
Pin–for–Pin Replacement for CD4034B.
ORDERING INFORMATION
MC14XXXBCP
MC14XXXBCL
MC14XXXBDW
Plastic
Ceramic
SOIC
•
T
A
= – 55° to 125°C for all packages.
MAXIMUM RATINGS* (Voltages Referenced to V
)
SS
Symbol
Parameter
DC Supply Voltage
Value
Unit
V
V
DD
– 0.5 to + 18.0
PIN ASSIGNMENT
V , V
in out
Input or Output Voltage (DC or Transient)
– 0.5 to V
DD
+ 0.5
V
B8
B7
B6
B5
B4
B3
1
2
3
4
5
6
24
23
22
21
20
19
V
DD
l , l
Input or Output Current (DC or Transient),
per Pin
± 10
mA
in out
A8
A7
A6
A5
A4
P
D
Power Dissipation, per Package†
Storage Temperature
500
mW
C
T
stg
– 65 to + 150
260
T
L
Lead Temperature (8–Second Soldering)
C
* Maximum Ratings are those values beyond which damage to the device may occur.
†Temperature Derating:
B2
B1
7
18
17
16
15
14
13
A3
A2
A1
C
Plastic “P and D/DW” Packages: – 7.0 mW/ C From 65 C To 125 C
Ceramic “L” Packages: – 12 mW/ C From 100 C To 125 C
8
A ENABLE
9
D
10
11
12
S
This device contains protection circuitry to guard against damage
due to high static voltages or electric fields. However, precautions must
be taken to avoid applications of any voltage higher than maximum rated
A/B
A/S
P/S
V
SS
voltages to this high-impedance circuit. For proper operation, V and
in
V
out
should be constrained to the range V
SS
≤ (V or V ) ≤ V .
in out DD
Unused inputs must always be tied to an appropriate logic voltage
level (e.g., either V or V ). Unused outputs must be left open.
SS DD
REV 3
1/94
Motorola, Inc. 1995
MOTOROLA CMOS LOGIC DATA
MC14034B
135