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MC14035B PDF预览

MC14035B

更新时间: 2024-11-18 22:58:11
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 移位寄存器
页数 文件大小 规格书
6页 227K
描述
4-Bit Parallel-In/Parallel-Out Shift Register

MC14035B 数据手册

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SEMICONDUCTOR TECHNICAL DATA  
L SUFFIX  
CERAMIC  
CASE 620  
The MC14035B 4–bit shift register is constructed with MOS P–channel  
and N–channel enhancement mode devices in a single monolithic structure.  
It consists of a 4–stage clocked serial–shift register with synchronous  
parallel inputs and buffered parallel outputs. The Parallel/Serial (P/S) input  
allows serial–right shifting of data or synchronous parallel loading via inputs  
P SUFFIX  
PLASTIC  
CASE 648  
D
thru D . The True/Complement (T/C) input determines whether the  
P0  
P3  
outputs display the Q or Q outputs of the flip–flop stages. J–K logic forms the  
serial input to the first stage. With the J and K inputs connected together they  
operate as a serial “D” input.  
D SUFFIX  
SOIC  
CASE 751B  
This device may be effectively used for shift–right/shift–left registers,  
parallel–to–serial/serial–to–parallel conversion, sequence generation, up/  
down Johnson or ring counters, pseudo–random code generation, frequen-  
cy and phase comparators, sample and hold registers, etc . . .  
ORDERING INFORMATION  
4–Stage Clocked Serial–Shift Operation  
Synchronous Parallel Loading of all Four Stages  
J–K Serial Inputs on First Stage  
Asynchronous True/Complement Control of all Outputs  
Fully Static Operation  
Asynchronous Master Reset  
Data Transfer Occurs on the Positive–Going Clock Transition  
No Limit on Clock Rise and Fall Times  
MC14XXXBCP  
MC14XXXBCL  
MC14XXXBD  
Plastic  
Ceramic  
SOIC  
T
A
= – 55° to 125°C for all packages.  
PIN ASSIGNMENT  
Q0  
1
2
16  
15  
V
DD  
All Inputs are Buffered  
Supply Voltage Range = 3.0 Vdc to 18 Vdc  
Capable of Driving Two Low–power TTL Loads or One Low–power  
Schottky TTL Load Over the Rated Temperature Range  
T/C  
Q1  
Q2  
Q3  
K
J
3
4
5
6
7
8
14  
13  
12  
11  
10  
9
MAXIMUM RATINGS* (Voltages Referenced to V  
)
SS  
R
D
D
D
D
P3  
P2  
P1  
P0  
Symbol  
Parameter  
DC Supply Voltage  
Value  
Unit  
V
C
V
DD  
– 0.5 to + 18.0  
P/S  
V , V  
in out  
Input or Output Voltage (DC or Transient)  
– 0.5 to V  
DD  
+ 0.5  
V
V
SS  
l , l  
in out  
Input or Output Current (DC or Transient),  
per Pin  
± 10  
mA  
P
Power Dissipation, per Package†  
Storage Temperature  
500  
mW  
C
D
T
stg  
– 65 to + 150  
260  
T
Lead Temperature (8–Second Soldering)  
C
L
* Maximum Ratings are those values beyond which damage to the device may occur.  
Temperature Derating:  
Plastic “P and D/DW” Packages: – 7.0 mW/ C From 65 C To 125 C  
Ceramic “L” Packages: – 12 mW/ C From 100 C To 125 C  
TRUTH TABLE  
Inputs  
t
Output  
Q
0
n
C
J
K
R
0
0
1
0
1
0
0
0
0
0
Q0 (n – 1)  
Q0 (n – 1)  
X = Don’t Care  
P/S = 0 = Serial Mode  
T/C = 1 = True Outputs  
1
X
X
1
X
X
0
0
1
1
Q0 (n – 1)  
0
X
REV 3  
1/94  
Motorola, Inc. 1995  

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