The MC14015B dual 4–bit static shift register is constructed with
MOS P–channel and N–channel enhancement mode devices in a
single monolithic structure. It consists of two identical, independent
4–state serial–input/parallel–output registers. Each register has
independent Clock and Reset inputs with a single serial Data input.
The register states are type D master–slave flip–flops. Data is shifted
from one stage to the next during the positive–going clock transition.
Each register can be cleared when a high level is applied on the Reset
line. These complementary MOS shift registers find primary use in
buffer storage and serial–to–parallel conversion where low power
dissipation and/or noise immunity is desired.
http://onsemi.com
MARKING
DIAGRAMS
16
PDIP–16
P SUFFIX
CASE 648
MC14015BCP
AWLYYWW
1
• Diode Protection on All Inputs
• Supply Voltage Range = 3.0 Vdc to 18 Vdc
• Logic Edge–Clocked Flip–Flop Design —
16
1
SOIC–16
D SUFFIX
CASE 751B
14015B
AWLYWW
Logic state is retained indefinitely with clock level either high or low;
information is transferred to the output only on the positive going
edge of the clock pulse.
16
• Capable of Driving Two Low–power TTL Loads or One Low–power
Schottky TTL Load Over the Rated Temperature Range.
TSSOP–16
DT SUFFIX
CASE 948F
14
015B
ALYW
1
MAXIMUM RATINGS (Voltages Referenced to V ) (Note 2.)
SS
16
1
Symbol
Parameter
Value
Unit
V
SOEIAJ–16
F SUFFIX
CASE 966
MC14015B
AWLYWW
V
DD
DC Supply Voltage Range
–0.5 to +18.0
V , V
in out
Input or Output Voltage Range
(DC or Transient)
–0.5 to V + 0.5
V
DD
A
= Assembly Location
I , I
in out
Input or Output Current
(DC or Transient) per Pin
±10
mA
WL or L = Wafer Lot
YY or Y = Year
P
D
Power Dissipation,
500
mW
WW or W = Work Week
per Package (Note 3.)
T
Ambient Temperature Range
Storage Temperature Range
–55 to +125
–65 to +150
260
°C
°C
°C
A
ORDERING INFORMATION
T
stg
Device
Package
PDIP–16
SOIC–16
Shipping
T
Lead Temperature
L
(8–Second Soldering)
MC14015BCP
MC14015BD
2000/Box
48/Rail
2. Maximum Ratings are those values beyond which damage to the device
may occur.
3. Temperature Derating:
MC14015BDR2
SOIC–16 2500/Tape & Reel
TSSOP–16 2000/Tape & Reel
Plastic “P and D/DW” Packages: – 7.0 mW/ C From 65 C To 125 C
MC14015BDT
MC14015BF
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
SOEIAJ–16
SOEIAJ–16
See Note 1.
See Note 1.
high–impedancecircuit. For proper operation, V and V should be constrained
in
out
MC14015BFEL
to the range V
(V or V
in
)
V
DD
.
SS
out
Unused inputs must always be tied to an appropriate logic voltage level (e.g.,
either V or V ). Unused outputs must be left open.
1. For ordering information on the EIAJ version of
the SOIC packages, please contact your local
ON Semiconductor representative.
SS
DD
Semiconductor Components Industries, LLC, 2000
1
Publication Order Number:
March, 2000 – Rev. 3
MC14015B/D