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MC14015BFELG PDF预览

MC14015BFELG

更新时间： 2024-01-19 13:08:15
品牌 Logo 应用领域
安森美 - ONSEMI 光电二极管输出元件逻辑集成电路触发器
页数 文件大小 规格书
10页 133K
描述
4000/14000/40000 SERIES, 4-BIT RIGHT SERIAL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, PDSO16, LEAD FREE, EIAJ, PLASTIC, SO-16

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MC14015BFELG 技术参数

是否Rohs认证： 符合生命周期：Obsolete
零件包装代码：SOIC包装说明：LEAD FREE, EIAJ, PLASTIC, SO-16
针数：16Reach Compliance Code：unknown
HTS代码：8542.39.00.01Factory Lead Time：1 week
风险等级：5.58计数方向：RIGHT
系列：4000/14000/40000JESD-30 代码：R-PDSO-G16
JESD-609代码：e4长度：10.2 mm
逻辑集成电路类型：SERIAL IN PARALLEL OUT最大频率@ Nom-Sup：1500000 Hz
湿度敏感等级：3位数：4
功能数量：2端子数量：16
最高工作温度：125 °C最低工作温度：-55 °C
输出极性：TRUE封装主体材料：PLASTIC/EPOXY
封装代码：SOP封装等效代码：SOP16,.3
封装形状：RECTANGULAR封装形式：SMALL OUTLINE
峰值回流温度（摄氏度）：260电源：5/15 V
传播延迟（tpd）：750 ns认证状态：Not Qualified
座面最大高度：2.05 mm子类别：Shift Registers
最大供电电压 (Vsup)：18 V最小供电电压 (Vsup)：3 V
标称供电电压 (Vsup)：5 V表面贴装：YES
技术：CMOS温度等级：MILITARY
端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)端子形式：GULL WING
端子节距：1.27 mm端子位置：DUAL
处于峰值回流温度下的最长时间：40触发器类型：POSITIVE EDGE
宽度：5.275 mm最小 fmax：3.75 MHz
Base Number Matches：1

MC14015BFELG 数据手册

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MC14015B  
Dual 4−Bit Static  
Shift Register  
The MC14015B dual 4−bit static shift register is constructed with  
MOS P−Channel and N−Channel enhancement mode devices in a  
single monolithic structure. It consists of two identical, independent  
4−state serial−input/parallel−output registers. Each register has  
independent Clock and Reset inputs with a single serial Data input.  
The register states are type D master−slave flip−flops. Data is shifted  
from one stage to the next during the positive−going clock transition.  
Each register can be cleared when a high level is applied on the Reset  
line. These complementary MOS shift registers find primary use in  
buffer storage and serial−to−parallel conversion where low power  
dissipation and/or noise immunity is desired.  
http://onsemi.com  
MARKING  
DIAGRAMS  
16  
1
PDIP−16  
P SUFFIX  
CASE 648  
MC14015BCP  
AWLYYWWG  
Features  
16  
• Diode Protection on All Inputs  
• Supply Voltage Range = 3.0 Vdc to 18 Vdc  
• Logic Edge−Clocked Flip−Flop Design  
SOIC−16  
D SUFFIX  
CASE 751B  
14015BG  
AWLYWW  
1
• Logic state is retained indefinitely with clock level either high or  
low; information is transferred to the output only on the positive  
going edge of the clock pulse  
16  
14  
015B  
ALYW  
TSSOP−16  
DT SUFFIX  
CASE 948F  
• Capable of Driving Two Low−power TTL Loads or One Low−power  
Schottky TTL Load Over the Rated Temperature Range  
• Pb−Free Packages are Available*  
1
MAXIMUM RATINGS (Voltages Referenced to V  
)
SS  
16  
1
Symbol  
Parameter  
Value  
Unit  
V
SOEIAJ−16  
F SUFFIX  
CASE 966  
V
DC Supply Voltage Range  
−0.5 to +18.0  
MC14015B  
ALYWG  
DD  
V , V  
in out  
Input or Output Voltage Range  
(DC or Transient)  
−0.5 to V + 0.5  
V
DD  
I , I  
in out  
Input or Output Current  
(DC or Transient) per Pin  
10  
mA  
A
WL, L  
YY, Y  
= Assembly Location  
= Wafer Lot  
P
Power Dissipation, per Package  
(Note 1)  
500  
mW  
D
= Year  
WW, W = Work Week  
T
Ambient Temperature Range  
Storage Temperature Range  
−55 to +125  
−65 to +150  
260  
°C  
°C  
°C  
A
G
= Pb−Free Indicator  
T
stg  
T
Lead Temperature  
(8−Second Soldering)  
L
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 2 of this data sheet.  
Maximum ratings are those values beyond which device damage can occur.  
Maximum ratings applied to the device are individual stress limit values (not  
normal operating conditions) and are not valid simultaneously. If these limits are  
exceeded, device functional operation is not implied, damage may occur and  
reliability may be affected.  
1. Temperature Derating:  
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C  
This device contains protection circuitry to guard against damage due to high  
static voltages or electric fields. However, precautions must be taken to avoid  
applications of any voltage higher than maximum rated voltages to this  
high−impedance circuit. For proper operation, V and V should be constrained  
*For additional information on our Pb−Free strategy  
and soldering details, please download the  
ON Semiconductor Soldering and Mounting  
Techniques Reference Manual, SOLDERRM/D.  
in  
out  
to the range V v (V or V ) v V  
.
DD  
SS  
in  
out  
Unused inputs must always be tied to an appropriate logic voltage level  
(e.g., either V or V ). Unused outputs must be left open.  
SS  
DD  
©
Semiconductor Components Industries, LLC, 2005  
1
Publication Order Number:  
August, 2005 − Rev. 6  
MC14015B/D  
 
1234567...10

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