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MC14016BDEBS

更新时间： 2024-09-28 13:11:15
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 开关
页数 文件大小 规格书
9页 273K
描述
SPST, 4 Func, CMOS, CDIP14

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MC14016BDEBS 技术参数

是否Rohs认证：不符合生命周期：Obsolete
Reach Compliance Code：unknown风险等级：5.92
Is Samacsys：N模拟集成电路 - 其他类型：SPST
JESD-30 代码：R-XDIP-T14JESD-609代码：e0
正常位置：NO功能数量：4
端子数量：14最高工作温度：125 °C
最低工作温度：-55 °C输出：SEPARATE OUTPUT
封装主体材料：CERAMIC封装代码：DIP
封装等效代码：DIP14,.3封装形状：RECTANGULAR
封装形式：IN-LINE电源：5/15 V
认证状态：Not Qualified筛选级别：MIL-STD-883 Class B (Modified)
子类别：Multiplexer or Switches表面贴装：NO
技术：CMOS温度等级：MILITARY
端子面层：Tin/Lead (Sn/Pb)端子形式：THROUGH-HOLE
端子节距：2.54 mm端子位置：DUAL
Base Number Matches：1

MC14016BDEBS 数据手册

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SEMICONDUCTOR TECHNICAL DATA  
L SUFFIX  
CERAMIC  
CASE 632  
The MC14016B quad bilateral switch is constructed with MOS P–channel  
and N–channel enhancement mode devices in a single monolithic structure.  
Each MC14016B consists of four independent switches capable of  
controlling either digital or analog signals. The quad bilateral switch is used  
in signal gating, chopper, modulator, demodulator and CMOS logic  
implementation.  
P SUFFIX  
PLASTIC  
CASE 646  
•
•
•
•
•
Diode Protection on All Inputs  
Supply Voltage Range = 3.0 Vdc to 18 Vdc  
Linearized Transfer Characteristics  
Low Noise — 12 nV/√Cycle, f ≥ 1.0 kHz typical  
Pin–for–Pin Replacements for CD4016B, CD4066B (Note improved  
transfer characteristic design causes more parasitic coupling  
capacitance than CD4016)  
D SUFFIX  
SOIC  
CASE 751A  
ORDERING INFORMATION  
MC14XXXBCP  
MC14XXXBCL  
MC14XXXBD  
Plastic  
Ceramic  
SOIC  
•
•
For Lower R  
MC14066B  
, Use The HC4016 High–Speed CMOS Device or The  
ON  
T
A
= – 55° to 125°C for all packages.  
This Device Has Inputs and Outputs Which Do Not Have ESD  
Protection. Antistatic Precautions Must Be Taken.  
MAXIMUM RATINGS* (Voltages Referenced to V  
)
SS  
BLOCK DIAGRAM  
Symbol  
Parameter  
DC Supply Voltage  
Value  
Unit  
V
V
DD  
– 0.5 to + 18.0  
13  
CONTROL 1  
2
3
V , V  
in out  
Input or Output Voltage (DC or Transient)  
– 0.5 to V  
DD  
+ 0.5  
V
OUT 1  
OUT 2  
OUT 3  
OUT 4  
1
5
l
in  
Input Current (DC or Transient),  
per Control Pin  
± 10  
mA  
IN 1  
CONTROL 2  
I
Switch Through Current  
± 25  
mA  
mW  
C
sw  
4
6
P
D
Power Dissipation, per Package†  
Storage Temperature  
500  
IN 2  
T
stg  
– 65 to + 150  
260  
CONTROL 3  
9
T
L
Lead Temperature (8–Second Soldering)  
C
8
* Maximum Ratings are those values beyond which damage to the device may occur.  
†Temperature Derating:  
IN 3  
12  
CONTROL 4  
Plastic “P and D/DW” Packages: – 7.0 mW/ C From 65 C To 125 C  
Ceramic “L” Packages: – 12 mW/ C From 100 C To 125 C  
10  
11  
IN 4  
This device contains protection circuitry to guard against damage  
due to high static voltages or electric fields. However, precautions must  
be taken to avoid applications of any voltage higher than maximum rated  
V
V
= PIN 14  
= PIN 7  
DD  
SS  
voltages to this high-impedance circuit. For proper operation, V and  
in  
V
should be constrained to the range V  
SS  
≤ (V or V ) ≤ V .  
in out DD  
out  
Unused inputs must always be tied to an appropriate logic voltage  
Control  
Switch  
Off  
level (e.g., either V  
SS  
or V ). Unused outputs must be left open.  
DD  
0 = V  
SS  
DD  
1 = V  
On  
LOGIC DIAGRAM  
(1/4 OF DEVICE SHOWN)  
OUT  
IN  
CONTROL  
LOGIC DIAGRAM RESTRICTIONS  
V
≤ V ≤ V  
SS  
in DD  
V
≤
V
≤ V  
SS  
out DD  
REV 3  
1/94  
Motorola, Inc. 1995  
1234567...9

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