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MC14015BCPT PDF预览

MC14015BCPT

更新时间: 2024-09-26 13:00:47
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 移位寄存器
页数 文件大小 规格书
8页 254K
描述
Shift Register, 4-Bit, CMOS, PDIP16

MC14015BCPT 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
包装说明:DIP, DIP16,.3Reach Compliance Code:unknown
风险等级:5.89JESD-30 代码:R-PDIP-T16
JESD-609代码:e0位数:4
功能数量:2端子数量:16
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:DIP
封装等效代码:DIP16,.3封装形状:RECTANGULAR
封装形式:IN-LINE电源:5/15 V
认证状态:Not Qualified子类别:Shift Registers
表面贴装:NO技术:CMOS
温度等级:INDUSTRIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUALBase Number Matches:1

MC14015BCPT 数据手册

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SEMICONDUCTOR TECHNICAL DATA  
L SUFFIX  
CERAMIC  
CASE 620  
The MC14015B dual 4–bit static shift register is constructed with MOS  
P–channel and N–channel enhancement mode devices in a single  
monolithic structure. It consists of two identical, independent 4–state  
serial–input/parallel–output registers. Each register has independent Clock  
and Reset inputs with a single serial Data input. The register states are type  
D master–slave flip–flops. Data is shifted from one stage to the next during  
the positive–going clock transition. Each register can be cleared when a high  
level is applied on the Reset line. These complementary MOS shift registers  
find primary use in buffer storage and serial–to–parallel conversion where  
low power dissipation and/or noise immunity is desired.  
P SUFFIX  
PLASTIC  
CASE 648  
D SUFFIX  
SOIC  
CASE 751B  
Diode Protection on All Inputs  
Supply Voltage Range = 3.0 Vdc to 18 Vdc  
Logic Edge–Clocked Flip–Flop Design —  
Logic state is retained indefinitely with clock level either high or low;  
information is transferred to the output only on the positive going edge  
of the clock pulse.  
Capable of Driving Two Low–power TTL Loads or One Low–power  
Schottky TTL Load Over the Rated Temperature Range.  
ORDERING INFORMATION  
MC14XXXBCP  
MC14XXXBCL  
MC14XXXBD  
Plastic  
Ceramic  
SOIC  
T
= – 55° to 125°C for all packages.  
A
MAXIMUM RATINGS* (Voltages Referenced to V  
)
SS  
Symbol  
Parameter  
DC Supply Voltage  
Value  
Unit  
V
BLOCK DIAGRAM  
V
DD  
– 0.5 to + 18.0  
Q0  
Q1  
Q2  
Q3  
5
V , V  
Input or Output Voltage (DC or Transient)  
– 0.5 to V  
DD  
+ 0.5  
V
in out  
7
D
C
4
l , l  
in out  
Input or Output Current (DC or Transient),  
per Pin  
± 10  
mA  
3
9
6
P
D
Power Dissipation, per Package†  
Storage Temperature  
500  
mW  
C
R
10  
T
stg  
– 65 to + 150  
260  
T
L
Lead Temperature (8–Second Soldering)  
C
Q0  
Q1  
Q2  
Q3  
13  
12  
11  
2
* Maximum Ratings are those values beyond which damage to the device may occur.  
Temperature Derating:  
15  
D
C
Plastic “P and D/DW” Packages: – 7.0 mW/ C From 65 C To 125 C  
Ceramic “L” Packages: – 12 mW/ C From 100 C To 125 C  
1
R
TRUTH TABLE  
14  
C
D
0
R
0
0
0
1
Q0  
Q
n
V
V
= PIN 16  
= PIN 8  
DD  
SS  
0
Q
Q
n–1  
n–1  
1
1
X
X
No Change  
0
No Change  
0
X
X = Don’t Care  
Q
Q
= Q0, Q1, Q2, or Q3, as applicable.  
n
= Output of prior stage.  
n–1  
REV 3  
1/94  
Motorola, Inc. 1995  

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