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MC14015B_14

更新时间： 2024-09-27 01:16:51
品牌 Logo 应用领域
安森美 - ONSEMI /
页数 文件大小 规格书
8页 111K
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Dual 4-Bit Static Shift Register

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MC14015B_14 数据手册

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MC14015B  
Dual 4-Bit Static  
Shift Register  
The MC14015B dual 4−bit static shift register is constructed with  
MOS P−Channel and N−Channel enhancement mode devices in  
a single monolithic structure. It consists of two identical, independent  
4−state serial−input/parallel−output registers. Each register has  
independent Clock and Reset inputs with a single serial Data input.  
The register states are type D master−slave flip−flops. Data is shifted  
from one stage to the next during the positive−going clock transition.  
Each register can be cleared when a high level is applied on the Reset  
line. These complementary MOS shift registers find primary use in  
buffer storage and serial−to−parallel conversion where low power  
dissipation and/or noise immunity is desired.  
http://onsemi.com  
SOIC−16  
D SUFFIX  
CASE 751B  
MARKING DIAGRAM  
Features  
16  
• Diode Protection on All Inputs  
14015BG  
AWLYWW  
• Supply Voltage Range = 3.0 Vdc to 18 Vdc  
• Logic Edge−Clocked Flip−Flop Design  
1
• Logic State is Retained Indefinitely with Clock Level either High or  
Low; Information is Transferred to the Output only on the  
Positive-going Edge of the Clock Pulse  
A
WL, L  
YY, Y  
= Assembly Location  
= Wafer Lot  
= Year  
• Capable of Driving Two Low−power TTL Loads or One Low−power  
Schottky TTL Load Over the Rated Temperature Range  
• NLV Prefix for Automotive and Other Applications Requiring  
Unique Site and Control Change Requirements; AEC−Q100  
Qualified and PPAP Capable  
WW, W = Work Week  
G
= Pb−Free Indicator  
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 2 of this data sheet.  
• This Device is Pb−Free and is RoHS Compliant  
MAXIMUM RATINGS (Voltages Referenced to V  
)
SS  
Symbol  
Parameter  
Value  
Unit  
V
V
DD  
DC Supply Voltage Range  
−0.5 to +18.0  
V , V  
in out  
Input or Output Voltage Range  
(DC or Transient)  
−0.5 to V + 0.5  
V
DD  
I , I  
in out  
Input or Output Current  
(DC or Transient) per Pin  
10  
mA  
P
T
Power Dissipation, per Package (Note 1)  
Ambient Temperature Range  
500  
mW  
°C  
D
−55 to +125  
−65 to +150  
260  
A
T
stg  
Storage Temperature Range  
°C  
T
Lead Temperature  
°C  
L
(8−Second Soldering)  
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality  
should not be assumed, damage may occur and reliability may be affected.  
1. Temperature Derating: “D/DW” Package: –7.0 mW/_C From 65_C To 125_C  
This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be  
taken to avoid applications of any voltage higher than maximum rated voltages to this high−impedance circuit. For proper operation, V and V  
in  
out  
should be constrained to the range V ≤ (V or V ) ≤ V .  
SS  
in  
out  
DD  
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either V or V ). Unused outputs must be left open.  
SS  
DD  
© Semiconductor Components Industries, LLC, 2014  
1
Publication Order Number:  
July, 2014 − Rev. 9  
MC14015B/D  
 
12345678

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