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MC10SX1125AD PDF预览

MC10SX1125AD

更新时间： 2024-11-14 19:55:55
品牌 Logo 应用领域
安森美 - ONSEMI ATM异步传输模式电信光电二极管电信集成电路
页数 文件大小 规格书
8页 95K
描述
ATM/SONET/SDH SUPPORT CIRCUIT, PDSO16, PLASTIC, SOIC-16

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中文翻译

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MC10SX1125AD 技术参数

生命周期：Obsolete零件包装代码：SOIC
包装说明：SOP,针数：16
Reach Compliance Code：unknownHTS代码：8542.39.00.01
风险等级：5.82JESD-30 代码：R-PDSO-G16
长度：9.9 mm功能数量：1
端子数量：16最高工作温度：85 °C
最低工作温度：-40 °C封装主体材料：PLASTIC/EPOXY
封装代码：SOP封装形状：RECTANGULAR
封装形式：SMALL OUTLINE认证状态：Not Qualified
座面最大高度：1.75 mm标称供电电压：5 V
表面贴装：YES电信集成电路类型：ATM/SONET/SDH SUPPORT CIRCUIT
温度等级：INDUSTRIAL端子形式：GULL WING
端子节距：1.27 mm端子位置：DUAL
宽度：3.9 mmBase Number Matches：1

MC10SX1125AD 数据手册

 浏览型号MC10SX1125AD的Datasheet PDF文件第2页浏览型号MC10SX1125AD的Datasheet PDF文件第3页浏览型号MC10SX1125AD的Datasheet PDF文件第4页浏览型号MC10SX1125AD的Datasheet PDF文件第5页浏览型号MC10SX1125AD的Datasheet PDF文件第6页浏览型号MC10SX1125AD的Datasheet PDF文件第7页 
The SX1125A is an integrated limiting amplifier for high frequency  
fiber optic applications. The device interfaces directly to the  
trans–impedance amplifier of a typical optical to electrical conversion  
portion of a fiber optic link. With data rate capabilities in the 622Mb/s  
range, the high gain limiting amplification of the SX1125A is ideal for  
high speed fiber optic applications like SONET/SDM, ATM, FDDI,  
Fibre Channel or Serial Hippi. The device is functionally and pin  
compatible to the Signetics SA5225 with a significantly higher  
http://onsemi.com  
MARKING  
DIAGRAM  
16  
SO–16  
D SUFFIX  
CASE 751B  
10SX1125A  
AWLYWW  
16  
bandwidth. The C  
and C inputs to the limiting amplifier  
1
AZP  
AZN  
1
provide an auto-zero function to effectively cancel any input offset  
voltage present in the amplifier.  
A
= Assembly Location  
WL = Wafer Lot  
= Year  
The SX1125A incorporates a programmable level detect function to  
identify when the input signal has been lost. This information can be  
fed back to the Disable input of the device to maintain stability under  
Y
WW = Work Week  
loss of signal conditions. Using the V pin the sensitivity of the level  
PIN ASSIGNMENT  
set  
detect can be adjusted. The C  
input so that random noise spikes are filtered out.  
input is used to filter the level detect  
LD  
V
set  
16  
V
V
D
D
out  
12  
GND LOS LOS  
E
ref CCE out  
15  
14  
13  
11  
10  
9
The MC10SX1125A is compatible with MECL10H logic levels.  
• Wideband Operation: 20kHz to 550MHz  
• Programmable Input Signal Level Detection  
• Operation with single +5V or standard ECL supply  
• Standard 16-lead SOIC Package  
1
2
3
4
5
6
7
8
C
C
GND  
D
in  
D
in  
V C Disable  
CCA LD  
• Fully Differential Design to Minimize Noise Affects  
• 10KH Compatible  
AZN AZP  
A
Pinout: 16-Lead Plastic Package  
(Top View)  
BLOCK DIAGRAM  
C
C
AZP AZN  
D
in  
D
out  
Limiting  
ECL  
ORDERING INFORMATION  
Amplifier  
Buffer  
D
out  
Device  
Package  
SO–16  
Shipping  
48 / Rail  
D
in  
MC10SX1125AD  
MC10SX1125ADR2  
SO–16  
2500 / Reel  
Disable  
Disable  
V
ref  
Reference  
LOS  
LOS  
Level  
Detect  
ECL  
Buffer  
V
set  
C
LD  
This document contains information on a product under development. ON Semiconductor  
reserves the right to change or discontinue this product without notice.  
Semiconductor Components Industries, LLC, 2000  
1
Publication Order Number:  
April, 2000 – Rev. 0  
MC10SX1125A/D  
12345678

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