The MC10H164 is a MECL 10H part which is a functional/pinout
duplication of the standard MECL 10K family part, with 100%
improvement in propagation delay, and no increase in power supply
current.
The MC10H164 is designed to be used in data multiplexing and
parallel to serial conversion applications. Full parallel gating provides
equal delays through any data path. The MC10H164 incorporates an
output buffer, eight inputs and an enable. A high on the enable forces
the output low. The open emitter output allows the MC10H164 to be
connected directly to a data bus. The enable line allows an easy means
of expanding to more than 8 lines using additional MC10H164’s.
• Propagation Delay, 1.0 ns Typical
http://onsemi.com
MARKING
DIAGRAMS
16
CDIP–16
L SUFFIX
CASE 620
MC10H164L
AWLYYWW
• Power Dissipation, 310 mW Typical (same as MECL 10K)
• Improved Noise Margin 150 mV (Over Operating Voltage and
Temperature Range)
• Voltage Compensated
• MECL 10K–Compatible
1
16
PDIP–16
P SUFFIX
CASE 648
MC10H164P
AWLYYWW
1
1
LOGIC DIAGRAM
A
B
7
PLCC–20
FN SUFFIX
CASE 775
V
=
=
=
PIN 1
PIN 16
PIN 8
CC1
10H164
9
V
CC2
AWLYYWW
V
EE
C
10
Enable 2
Z
15
X0
6
A
= Assembly Location
X1 5
X2 4
WL = Wafer Lot
YY = Year
WW = Work Week
X3 3
X4 11
TRUTH TABLE
X5 12
X6 13
X7 14
ADDRESS INPUTS
ENABLE
C
B
A
Z
L
L
L
L
L
L
L
L
L
L
H
H
L
H
L
X0
X1
X2
X3
H
L
L
L
L
H
H
H
H
X
L
L
H
H
X
L
H
L
H
X
X4
X5
X6
X7
L
DIP PIN ASSIGNMENT
V
V
CC2
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
CC1
H
ENABLE
X3
Z
X7
X6
X5
X4
C
X2
X1
ORDERING INFORMATION
X0
A
Device
Package
Shipping
V
EE
B
MC10H164L
CDIP–16
25 Units/Rail
Pin assignment is for Dual–in–Line Package.
For PLCC pin assignment, see the Pin Conversion Tables on page 18
of the ON Semiconductor MECL Data Book (DL122/D).
MC10H164P
PDIP–16
PLCC–20
25 Units/Rail
46 Units/Rail
MC10H164FN
Semiconductor Components Industries, LLC, 2000
1
Publication Order Number:
March, 2000 – Rev. 7
MC10H164/D