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MC10H116_06

更新时间： 2024-11-06 05:10:23
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安森美 - ONSEMI /
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6页 163K
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Triple Line Receiver

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MC10H116_06 数据手册

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MC10H116  
Triple Line Receiver  
Description  
The MC10H116 is a triple differential amplifier designed for use in  
sensing differential signals over long lines and is a functional/pinout  
duplication of the MC10116, with 100% improvement in propagation  
delay and no increase in power supply current. For termination  
information see AND8020.  
http://onsemi.com  
MARKING DIAGRAMS*  
Features  
• Propagation Delay, 1.0 ns Typical  
• Power Dissipation 85 mW Typ/Pkg (same as MECL 10K™)  
• Improved Noise Margin 150 mV (Over Operating Voltage and  
Temperature Range)  
16  
1
16  
MC10H116L  
AWLYYWW  
1
CDIP−16  
L SUFFIX  
• Voltage Compensated  
CASE 620A  
• MECL 10K Compatible  
• Pb−Free Packages are Available*  
16  
1
MC10H116P  
AWLYYWWG  
4
5
2
3
*V to be used to supply bias to the MC10H116 only and bypassed  
BB  
16  
(when used) with 0.01 mF to 0.1 mF capacitor to ground (0 V). V can  
BB  
source < 1.0 mA.  
1
The MC10H116 is designed to be used in sensing differential signals  
9
6
7
PDIP−16  
P SUFFIX  
CASE 648  
over long lines. The bias supply (V ) is made available to make the  
BB  
10  
device useful as a Schmitt trigger, or in other applications where a  
stable reference voltage is necessary.  
12  
13  
14  
Active current sources provide these receivers with excellent  
common−mode noise rejection. If any amplifier in a package is not  
used, one input of that amplifier must be connected to V to prevent  
15  
11  
1 20  
BB  
unbalancing the current−source bias network.  
The MC10H116 does not have internal−input pull− down resistors.  
This provides high impedance to the amplifier input and facilitates  
differential connections.  
V
*
BB  
V
V
V
= Pin 1  
= Pin 16  
= Pin 8  
CC1  
20  
1
CC2  
10H116G  
AWLYYWW  
Applications:  
EE  
• Low Level Receiver  
• Voltage Level  
Interface  
PLCC−20  
FN SUFFIX  
CASE 775  
When input pin with  
bubble goes positive  
it’s respective output  
pin with bubble goes  
positive.  
• Schmitt Trigger  
16  
Figure 1. Logic Diagram  
16  
10H116G  
AWLYWW  
1
SO−16  
D SUFFIX  
CASE 751B  
1
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
V
V
CC2  
CC1  
OUT  
OUT  
16  
A
A
C
C
C
C
OUT  
OUT  
IN  
16  
10H116  
ALYWG  
1
A
A
IN  
IN  
SOEIAJ−16  
M, MEL SUFFIX  
CASE 966  
IN  
B
B
V
B
B
OUT  
OUT  
BB  
IN  
1
A
= Assembly Location  
= Wafer Lot  
V
IN  
EE  
WL  
YY  
WW  
= Year  
Pin assignment is for Dual−in−Line Package.  
For PLCC pin assignment, see TND309, the Pin Conversion Tables,  
page 9.  
= Work Week  
*For additional marking information, refer to  
Application Note AND8002/D.  
Figure 2. Dip Pin Assignment  
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 3 of this data sheet.  
*For additional information on our Pb−Free strategy and soldering details, please  
download the ON Semiconductor Soldering and Mounting Techniques  
Reference Manual, SOLDERRM/D.  
©
Semiconductor Components Industries, LLC, 2006  
1
Publication Order Number:  
February, 2006 − Rev. 10  
MC10H116/D  
123456

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