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MC10EPT20D PDF预览

MC10EPT20D

更新时间: 2024-01-05 16:21:59
品牌 Logo 应用领域
安森美 - ONSEMI 锁存器接口集成电路光电二极管
页数 文件大小 规格书
4页 68K
描述
LVTTL/LVCMOS to Differential LVPECL Translator

MC10EPT20D 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:SOIC包装说明:SOP, SOP8,.25
针数:8Reach Compliance Code:not_compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
Factory Lead Time:1 week风险等级:5.14
最大延迟:0.45 ns接口集成电路类型:TTL/CMOS TO PECL TRANSLATOR
JESD-30 代码:R-PDSO-G8JESD-609代码:e0
长度:4.9 mm位数:1
功能数量:1端子数量:8
最高工作温度:85 °C最低工作温度:-40 °C
输出特性:OPEN-EMITTER输出锁存器或寄存器:NONE
输出极性:COMPLEMENTARY封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP8,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
峰值回流温度(摄氏度):240电源:3.3 V
认证状态:Not Qualified座面最大高度:1.75 mm
子类别:Level Translators最大供电电压:3.6 V
最小供电电压:3 V标称供电电压:3.3 V
表面贴装:YES技术:ECL
温度等级:INDUSTRIAL端子面层:Tin/Lead (Sn80Pb20)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:30
宽度:3.9 mmBase Number Matches:1

MC10EPT20D 数据手册

 浏览型号MC10EPT20D的Datasheet PDF文件第2页浏览型号MC10EPT20D的Datasheet PDF文件第3页浏览型号MC10EPT20D的Datasheet PDF文件第4页 
The MC10EPT20 is a LVTTL/LVCMOS to differential LVPECL  
translator. Because LVPECL (Positive ECL) levels are used only  
+3.3V and ground are required. The small outline 8–lead SOIC  
package and the single gate of the EPT20 makes it ideal for those  
applications where space, performance, and low power are at a  
premium.  
http://onsemi.com  
390ps Typical Propagation Delay  
High Bandwidth to 1.0 GHz Typical  
Differential LVPECL Outputs  
Small Outline SOIC Package  
PNP LVTTL Inputs for Minimal Loading  
8
1
SO–8  
D SUFFIX  
CASE 751  
V Range of 3.0V to 3.6V  
CC  
ESD Protection: >1.5KV HBM, >200V MM  
Q Output will default HIGH with inputs open  
MARKING DIAGRAM  
Moisture Sensitivity Level 1, Indefinite Time Out of Drypack.  
For Additional Information, See Application Note AND8003/D  
Flammability Rating: UL–94 code V–0 @ 1/8”,  
Oxygen Index 28 to 34  
8
1
A = Assembly Location  
L = Wafer Lot  
Y = Year  
HPT20  
ALYW  
W = Work Week  
Transistor Count = 150 devices  
*For additional information, see Application Note  
AND8002/D  
NC  
Q
1
2
8
7
V
CC  
PIN DESCRIPTION  
PIN  
Q, Q  
D
FUNCTION  
Differential LVPECL Outputs  
LVTTL Input  
LVTTL  
D
V
CC  
Positive Supply  
GND  
Ground  
Q
3
4
6
5
NC  
GND  
LVPECL  
NC  
ORDERING INFORMATION  
Device  
Package  
Shipping  
MC10EPT20D  
SOIC  
98 Units/Rail  
Figure 1. 8–Lead Pinout (Top View) and Logic Diagram  
MC10EPT20DR2  
SOIC  
2500 Tape & Reel  
Semiconductor Components Industries, LLC, 1999  
1
Publication Order Number:  
September, 1999 – Rev. 1.0  
MC10EPT20/D  

MC10EPT20D 替代型号

型号 品牌 替代类型 描述 数据表
MC100EPT20DTR2G ONSEMI

完全替代

3.3V LVTTL/LVCMOS to Differential LVPECL Translator
MC100EPT20DR2G ONSEMI

完全替代

3.3V LVTTL/LVCMOS to Differential LVPECL Translator
MC10ELT20DR2G ONSEMI

完全替代

5VTTL to Differential PECL Translator

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