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MC10EPT20DR2

更新时间： 2024-01-01 22:04:33

品牌	Logo	应用领域
安森美 - ONSEMI		/
页数	文件大小	规格书
4页	68K
描述
LVTTL/LVCMOS to Differential LVPECL Translator

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中文翻译

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数据手册

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MC10EPT20DR2 数据手册

The MC10EPT20 is a LVTTL/LVCMOS to differential LVPECL

translator. Because LVPECL (Positive ECL) levels are used only

+3.3V and ground are required. The small outline 8–lead SOIC

package and the single gate of the EPT20 makes it ideal for those

applications where space, performance, and low power are at a

premium.

http://onsemi.com

• 390ps Typical Propagation Delay

• High Bandwidth to 1.0 GHz Typical

• Differential LVPECL Outputs

• Small Outline SOIC Package

• PNP LVTTL Inputs for Minimal Loading

SO–8

D SUFFIX

CASE 751

• V Range of 3.0V to 3.6V

• ESD Protection: >1.5KV HBM, >200V MM

• Q Output will default HIGH with inputs open

MARKING DIAGRAM

• Moisture Sensitivity Level 1, Indefinite Time Out of Drypack.

For Additional Information, See Application Note AND8003/D

• Flammability Rating: UL–94 code V–0 @ 1/8”,

Oxygen Index 28 to 34

A = Assembly Location

L = Wafer Lot

Y = Year

HPT20

ALYW

W = Work Week

• Transistor Count = 150 devices

*For additional information, see Application Note

AND8002/D

PIN DESCRIPTION

Q, Q

FUNCTION

Differential LVPECL Outputs

LVTTL Input

LVTTL

Positive Supply

GND

Ground

GND

LVPECL

ORDERING INFORMATION

Device

Package

Shipping

MC10EPT20D

SOIC

98 Units/Rail

Figure 1. 8–Lead Pinout (Top View) and Logic Diagram

MC10EPT20DR2

SOIC

2500 Tape & Reel

Semiconductor Components Industries, LLC, 1999

Publication Order Number:

September, 1999 – Rev. 1.0

MC10EPT20/D

12 3 4

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