MC10EPT20DTR2

更新时间： 2024-01-10 23:05:14

品牌	Logo	应用领域
安森美 - ONSEMI		/
页数	文件大小	规格书
8页	69K
描述
3.3VLVTTL/LVCMOS to Differential LVPECL Translator

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替代型号

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MC10EPT20DTR2 数据手册

MC10EPT20, MC100EPT20

3.3VꢀLVTTL/LVCMOS to

Differential LVPECL

Translator

The MC10EPT20 is a 3.3 V TTL/CMOS to differential PECL

translator. Because PECL (Positive ECL) levels are used, only +3.3 V

and ground are required. The small outline SOIC−8 package and the

single gate of the EPT20 makes it ideal for those applications where

space, performance, and low power are at a premium.

http://onsemi.com

MARKING DIAGRAMS*

The 100 Series contains temperature compensation.

HPT20

ALYW

KPT20

ALYW

• 390 ps Typical Propagation Delay

• Maximum Input Clock Frequency > 1 GHz Typical

SO−8

• Operating Range V = 3.0 V to 3.6 V

D SUFFIX

CASE 751

with GND = 0 V

• PNP TTL Input for Minimal Loading

• Q Output will Default HIGH with Input Open

• Pb−Free Packages are Available

HA20

ALYW

KA20

ALYW

TSSOP−8

DT SUFFIX

CASE 948R

L = Wafer Lot

Y = Year

H = MC10

K = MC100

W = Work Week

A = Assembly Location

*For additional marking information, refer to

Application Note AND8002/D.

ORDERING INFORMATION

See detailed ordering and shipping information in the package

dimensions section on page 6 of this data sheet.

Semiconductor Components Industries, LLC, 2004

Publication Order Number:

September, 2004 − Rev. 7

MC10EPT20/D

12 3 4 5 6 7 8

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MC10EPT20DTR2 替代型号

型号	品牌	替代类型	描述	数据表
MC100EPT20DTR2G	ONSEMI	完全替代	3.3V LVTTL/LVCMOS to Differential LVPECL Translator
MC100EPT20DTG	ONSEMI	完全替代	3.3VLVTTL/LVCMOS to Differential LVPECL Translator
MC100EPT20DG	ONSEMI	完全替代	3.3VLVTTL/LVCMOS to Differential LVPECL Translator

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