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MC10EPT20DG PDF预览

MC10EPT20DG

更新时间: 2024-01-08 03:05:33
品牌 Logo 应用领域
安森美 - ONSEMI /
页数 文件大小 规格书
10页 141K
描述
3.3V LVTTL/LVCMOS to Differential LVPECL Translator

MC10EPT20DG 技术参数

是否无铅: 不含铅生命周期:Active
零件包装代码:SOIC包装说明:SOP, SOP8,.25
针数:8Reach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
Factory Lead Time:1 week风险等级:1.33
最大延迟:0.45 ns接口集成电路类型:TTL/CMOS TO PECL TRANSLATOR
JESD-30 代码:R-PDSO-G8JESD-609代码:e3
长度:4.9 mm湿度敏感等级:1
位数:1功能数量:1
端子数量:8最高工作温度:85 °C
最低工作温度:-40 °C输出锁存器或寄存器:NONE
输出极性:COMPLEMENTARY封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP8,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
峰值回流温度(摄氏度):260电源:3.3 V
认证状态:Not Qualified座面最大高度:1.75 mm
子类别:Level Translators最大供电电压:3.6 V
最小供电电压:3 V标称供电电压:3.3 V
表面贴装:YES技术:ECL
温度等级:INDUSTRIAL端子面层:Tin (Sn)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:40
宽度:3.9 mmBase Number Matches:1

MC10EPT20DG 数据手册

 浏览型号MC10EPT20DG的Datasheet PDF文件第2页浏览型号MC10EPT20DG的Datasheet PDF文件第3页浏览型号MC10EPT20DG的Datasheet PDF文件第4页浏览型号MC10EPT20DG的Datasheet PDF文件第5页浏览型号MC10EPT20DG的Datasheet PDF文件第6页浏览型号MC10EPT20DG的Datasheet PDF文件第7页 
MC10EPT20, MC100EPT20  
3.3VꢀLVTTL/LVCMOS to  
Differential LVPECL  
Translator  
The MC10EPT20 is a 3.3 V TTL/CMOS to differential PECL  
translator. Because PECL (Positive ECL) levels are used, only +3.3 V  
and ground are required. The small outline SOIC8 package and the  
single gate of the EPT20 makes it ideal for those applications where  
space, performance, and low power are at a premium.  
http://onsemi.com  
MARKING DIAGRAMS*  
The 100 Series contains temperature compensation.  
8
1
8
8
HPT20  
ALYW  
G
KPT20  
ALYW  
G
Features  
1
SO8  
390 ps Typical Propagation Delay  
Maximum Input Clock Frequency > 1 GHz Typical  
1
D SUFFIX  
CASE 751  
Operating Range V = 3.0 V to 3.6 V  
CC  
with GND = 0 V  
8
1
8
8
PNP TTL Input for Minimal Loading  
Q Output will Default HIGH with Input Open  
PbFree Packages are Available  
1
HA20  
KA20  
ALYWG  
ALYWG  
TSSOP8  
DT SUFFIX  
CASE 948R  
G
G
1
1
4
1
4
DFN8  
MN SUFFIX  
CASE 506AA  
H
K
= MC10  
= MC100  
A
L
= Assembly Location  
= Wafer Lot  
5W = MC10  
3Q = MC100  
Y
W
G
= Year  
= Work Week  
= PbFree Package  
M
= Date Code  
(Note: Microdot may be in either location)  
*For additional marking information, refer to  
Application Note AND8002/D.  
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 7 of this data sheet.  
© Semiconductor Components Industries, LLC, 2006  
1
Publication Order Number:  
December, 2006 Rev. 9  
MC10EPT20/D  

MC10EPT20DG 替代型号

型号 品牌 替代类型 描述 数据表
MC100EPT20DTR2G ONSEMI

完全替代

3.3V LVTTL/LVCMOS to Differential LVPECL Translator
MC10EPT20DTG ONSEMI

完全替代

3.3V LVTTL/LVCMOS to Differential LVPECL Translator
MC100EPT20DTG ONSEMI

完全替代

3.3VLVTTL/LVCMOS to Differential LVPECL Translator

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