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MC10EP142FAR2 PDF预览

MC10EP142FAR2

更新时间: 2024-11-05 04:11:31
品牌 Logo 应用领域
安森美 - ONSEMI 移位寄存器
页数 文件大小 规格书
13页 176K
描述
3.3 V / 5 V ECL 9-Bit Shift Register

MC10EP142FAR2 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:QFP包装说明:LQFP, QFP32,.35SQ,32
针数:32Reach Compliance Code:not_compliant
HTS代码:8542.39.00.01风险等级:5.62
Is Samacsys:N其他特性:ECL MODE: VCC = 0V WITH VEE = -3V TO -5.5V; SIPO OPERATION ALSO AVAILABLE
计数方向:RIGHT系列:10E
JESD-30 代码:S-PQFP-G32JESD-609代码:e0
长度:7 mm逻辑集成电路类型:PARALLEL IN PARALLEL OUT
最大频率@ Nom-Sup:3000000000 Hz位数:9
功能数量:1端子数量:32
最高工作温度:85 °C最低工作温度:-40 °C
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:LQFP封装等效代码:QFP32,.35SQ,32
封装形状:SQUARE封装形式:FLATPACK, LOW PROFILE
峰值回流温度(摄氏度):240电源:+-3.3/+-5 V
传播延迟(tpd):0.8 ns认证状态:Not Qualified
座面最大高度:1.6 mm子类别:Shift Registers
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):3 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:ECL温度等级:INDUSTRIAL
端子面层:Tin/Lead (Sn80Pb20)端子形式:GULL WING
端子节距:0.8 mm端子位置:QUAD
处于峰值回流温度下的最长时间:30触发器类型:POSITIVE EDGE
宽度:7 mm最小 fmax:3000 MHz
Base Number Matches:1

MC10EP142FAR2 数据手册

 浏览型号MC10EP142FAR2的Datasheet PDF文件第2页浏览型号MC10EP142FAR2的Datasheet PDF文件第3页浏览型号MC10EP142FAR2的Datasheet PDF文件第4页浏览型号MC10EP142FAR2的Datasheet PDF文件第5页浏览型号MC10EP142FAR2的Datasheet PDF文件第6页浏览型号MC10EP142FAR2的Datasheet PDF文件第7页 
MC10EP142, MC100EP142  
3.3 V / 5 VꢀECL 9−Bit Shift  
Register  
The MC10EP/100EP142 is a 9bit shift register, designed with  
byte-parity applications in mind. The MC10/100EP142 is capable of  
performing serial/parallel data into serial/parallel out and shifting in  
only one direction. The nine inputs D0 D8 accept parallel input data,  
while SIN accepts serial input data. The QT0:87 outputs do not need  
to be terminated for the shift operation to function. To minimize  
power, any Q output not used should be left unterminated.  
The SEL (Select) input pin is used to switch between the two modes  
of operation SHIFT and LOAD. The shift direction is from Bit 0 to  
Bit 8. Input data is accepted by the registers a setup time before the  
positive going edge of CLK0 or CLK1; shifting is also accomplished  
on the positive clock edge. A HIGH on the Master Reset pin (MR)  
asynchronously resets all the registers to zero, overriding CLK0 and  
CLK1 inputs.  
http://onsemi.com  
MARKING  
DIAGRAM*  
MCxxx  
EP142  
AWLYYWWG  
LQFP32  
FA SUFFIX  
CASE 873A  
32  
The 100 Series contains temperature compensation.  
1
Features  
1
Shift Frequency >2.8 GHz (Typical)  
9-Bit for ByteParity Applications  
Asynchronous Master Reset  
Dual Clocks  
MCxxx  
EP142  
32  
1
AWLYYWWG  
QFN32  
MN SUFFIX  
CASE 488AM  
G
PECL Mode Operating Range: V = 3.0 V to 5.5 V  
CC  
with V = 0 V  
EE  
xxx  
A
= 10 or 100  
NECL Mode Operating Range: V = 0 V  
CC  
= Assembly Location  
with V = 3.0 V to 5.5 V  
EE  
WL, L = Wafer Lot  
Open Input Default State  
Safety Clamp on Inputs  
PbFree Packages are Available  
YY, Y  
= Year  
WW, W = Work Week  
G or G = PbFree Package  
(Note: Microdot may be in either location)  
*For additional marking information, refer to  
Application Note AND8002/D.  
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 11 of this data sheet.  
©
Semiconductor Components Industries, LLC, 2006  
1
Publication Order Number:  
November, 2006 Rev. 16  
MC10EP142/D  

MC10EP142FAR2 替代型号

型号 品牌 替代类型 描述 数据表
MC100EP142FAR2G ONSEMI

完全替代

3.3 V / 5 V ECL 9-Bit Shift Register
MC10EP142MNR4G ONSEMI

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MC10EP142MNG ONSEMI

类似代替

3.3 V / 5 V ECL 9-Bit Shift Register

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