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MC10EP16DR2 PDF预览

MC10EP16DR2

更新时间: 2024-09-14 22:20:23
品牌 Logo 应用领域
安森美 - ONSEMI /
页数 文件大小 规格书
8页 91K
描述
Differential Receiver

MC10EP16DR2 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:SOIC包装说明:SOP, SOP8,.25
针数:8Reach Compliance Code:not_compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
Factory Lead Time:1 week风险等级:7.62
其他特性:CAN ALSO OPERATE WITH -3V TO -5.5V SUPPLY IN NECL MODE差分输出:YES
驱动器位数:1输入特性:DIFFERENTIAL
接口集成电路类型:LINE TRANSCEIVER接口标准:GENERAL PURPOSE
JESD-30 代码:R-PDSO-G8JESD-609代码:e0
长度:4.9 mm标称负供电电压:-5.2 V
功能数量:1端子数量:8
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装等效代码:SOP8,.25封装形状:RECTANGULAR
封装形式:SMALL OUTLINE峰值回流温度(摄氏度):240
电源:-5.2 V认证状态:Not Qualified
最大接收延迟:0.28 ns接收器位数:1
座面最大高度:1.75 mm子类别:Line Driver or Receivers
最大压摆率:32 mA最大供电电压:5.5 V
最小供电电压:3 V标称供电电压:3.3 V
表面贴装:YES技术:ECL
温度等级:INDUSTRIAL端子面层:Tin/Lead (Sn80Pb20)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:30
最大传输延迟:0.28 ns宽度:3.9 mm
Base Number Matches:1

MC10EP16DR2 数据手册

 浏览型号MC10EP16DR2的Datasheet PDF文件第2页浏览型号MC10EP16DR2的Datasheet PDF文件第3页浏览型号MC10EP16DR2的Datasheet PDF文件第4页浏览型号MC10EP16DR2的Datasheet PDF文件第5页浏览型号MC10EP16DR2的Datasheet PDF文件第6页浏览型号MC10EP16DR2的Datasheet PDF文件第7页 
The MC10EP16 is a differential receiver. The device is functionally  
equivalent to the EL16 and LVEL16 devices with higher performance  
capabilities. With output transition times significantly faster than the  
EL16 and LVEL16, the EP16 is ideally suited for interfacing with high  
frequency sources.  
http://onsemi.com  
The EP16 provides a V  
DC bias for AC coupling to the device within the package. The V  
output for either single-ended use or as a  
BB  
BB  
pin should be used only as a bias for the EP16 as its current sink/source  
capability is limited. Whenever used, the V  
to ground via a 0.01µf capacitor.  
pin should be bypassed  
BB  
8
1
160ps Propagation Delay  
High Bandwidth to 3 GHz Typical  
PECL mode: 3.0V to 5.5V V  
SO–8  
D SUFFIX  
CASE 751  
with V = 0V  
CC  
EE  
ECL mode: 0V V  
CC  
with V = –3.0V to –5.5V  
EE  
Internal Input Resistors: Pulldown on D, Pulldown and Pullup on D  
MARKING DIAGRAM  
Q Output will default LOW with inputs open or at V  
ESD Protection: 4KV HBM, 200V MM  
EE  
8
1
A = Assembly Location  
L = Wafer Lot  
Y = Year  
V Output  
HEP16  
ALYW  
BB  
New Differential Input Common Mode Range  
Moisture Sensitivity Level 1, Indefinite Time Out of Drypack.  
For Additional Information, See Application Note AND8003/D  
Flammability Rating: UL–94 code V–0 @ 1/8”,  
Oxygen Index 28 to 34  
W = Work Week  
*For additional information, see Application Note  
AND8002/D  
Transistor Count: 167 devices  
PIN DESCRIPTION  
PIN  
D, D  
Q, Q  
FUNCTION  
ECL Data Inputs  
ECL Data Outputs  
NC  
D
1
2
8
7
V
CC  
V
BB  
Ref. Voltage Output  
36.5k  
Q
Q
75k  
ORDERING INFORMATION  
D
3
4
6
5
Device  
Package  
Shipping  
75k  
MC10EP16D  
SOIC  
98 Units/Rail  
MC10EP16DR2  
SOIC  
2500 Tape & Reel  
V
V
EE  
BB  
Figure 1. 8–Lead Pinout (Top View) and Logic Diagram  
Semiconductor Components Industries, LLC, 1999  
1
Publication Order Number:  
September, 1999 – Rev. 1.0  
MC10EP16/D  

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