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MC10211LDS PDF预览

MC10211LDS

更新时间: 2024-11-23 13:11:15
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA
页数 文件大小 规格书
5页 106K
描述
NOR Gate, ECL10K, CDIP16

MC10211LDS 技术参数

是否Rohs认证:不符合生命周期:Obsolete
包装说明:DIP, DIP16,.3Reach Compliance Code:unknown
风险等级:5.85Is Samacsys:N
JESD-30 代码:R-XDIP-T16JESD-609代码:e0
逻辑集成电路类型:NOR GATE端子数量:16
最高工作温度:85 °C最低工作温度:-30 °C
封装主体材料:CERAMIC封装代码:DIP
封装等效代码:DIP16,.3封装形状:RECTANGULAR
封装形式:IN-LINE电源:-5.2 V
施密特触发器:NO子类别:Gates
表面贴装:NO技术:ECL10K
温度等级:OTHER端子面层:Tin/Lead (Sn/Pb)
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUALBase Number Matches:1

MC10211LDS 数据手册

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SEMICONDUCTOR TECHNICAL DATA  
The MC10211 is designed to drive up to six transmission lines simul–  
taneously. The multiple outputs of this device also allow the wire “OR”–ing of  
several levels of gating for minimization of gate and package count.  
The ability to control three parallel lines with minimum propagation delay  
from a single point makes the MC10211 particularly useful in clock distribution  
applications where minimum clock skew is desired.  
L SUFFIX  
CERAMIC PACKAGE  
CASE 620–10  
P
= 160 mW typ/pkg (No Loads)  
= 1.5 ns typ (All Output Loaded)  
D
P SUFFIX  
PLASTIC PACKAGE  
CASE 648–08  
t
pd  
t , t = 1.5 ns typ (20%–80%)  
r f  
FN SUFFIX  
PLCC  
CASE 775–02  
LOGIC DIAGRAM  
2
3
4
5
6
7
DIP  
PIN ASSIGNMENT  
12  
13  
14  
9
10  
11  
V
A
V
V
B
B
B
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
CC1  
CC2  
CC1  
OUT  
OUT  
OUT  
OUT  
OUT  
OUT  
A
A
V
V
V
= PIN 1, 15  
= PIN 16  
= PIN 8  
CC1  
CC2  
EE  
A
IN  
B
B
B
A
IN  
IN  
IN  
IN  
A
IN  
V
EE  
Pin assignment is for Dual–in–Line Package.  
For PLCC pin assignment, see the Pin Conversion  
Tables on page 6–36 of the Motorola MECL Data  
Book (DL122/D).  
3/93  
Motorola, Inc. 1996  
REV 5  

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