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MC10212 PDF预览

MC10212

更新时间: 2024-11-19 04:41:03
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA
页数 文件大小 规格书
5页 74K
描述
High Speed Dual 3-Input/3-Output OR/NOR Gate

MC10212 数据手册

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SEMICONDUCTOR TECHNICAL DATA  
The MC10212 is designed to drive up to six transmission lines simul–  
taneously. The multiple outputs of this device also allow the wire “OR”–ing of  
several levels of gating for minimization of gate and package count.  
The ability to control three parallel lines with minimum propagation delay  
from a single point makes the MC10212 particularly useful in clock distribution  
applications where minimum clock skew is desired.  
L SUFFIX  
CERAMIC PACKAGE  
CASE 620–10  
P
= 160 mW typ/pkg (No Load)  
= 1.5 ns typ (All Outputs Loaded)  
D
P SUFFIX  
PLASTIC PACKAGE  
CASE 648–08  
t
pd  
t , t = 1.5 ns typ (20%–80%)  
r f  
FN SUFFIX  
PLCC  
CASE 775–02  
LOGIC DIAGRAM  
4
3
DIP  
5
6
7
2
PIN ASSIGNMENT  
12  
13  
14  
V
A
V
V
B
B
B
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
CC1  
CC2  
CC1  
OUT  
OUT  
OUT  
9
10  
11  
OUT  
OUT  
OUT  
A
A
V
V
V
= PIN 1, 15  
= PIN 16  
= PIN 8  
CC1  
CC2  
EE  
A
IN  
B
B
B
A
IN  
IN  
IN  
IN  
A
IN  
V
EE  
Pin assignment is for Dual–in–Line Package.  
For PLCC pin assignment, see the Pin Conversion  
Tables on page 6–11 of the Motorola MECL Data  
Book (DL122/D).  
3/93  
Motorola, Inc. 1996  
REV 5  

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