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MC100LVEL11_06 PDF预览

MC100LVEL11_06

更新时间: 2024-01-31 02:36:33
品牌 Logo 应用领域
安森美 - ONSEMI /
页数 文件大小 规格书
8页 142K
描述
3.3V ECL 1:2 Differential Fanout Buffer

MC100LVEL11_06 数据手册

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MC100LVEL11  
3.3VꢀECL 1:2  
Differential Fanout Buffer  
Description  
The MC100LVEL11 is a differential 1:2 fanout buffer. The device is  
functionally similar to the E111 device but with higher performance  
capabilities. Having within-device skews and output transition times  
significantly improved over the E111, the LVEL11 is ideally suited for  
those applications which require the ultimate in AC performance.  
The differential inputs of the LVEL11 employ clamping circuitry to  
maintain stability under open input conditions. If the inputs are left open  
http://onsemi.com  
MARKING  
DIAGRAMS*  
8
8
(pulled to V ) the Q outputs will go LOW.  
EE  
1
KVL11  
ALYW  
G
Features  
330 ps Propagation Delay  
5 ps Skew Between Outputs  
High Bandwidth Output Transitions  
The 100 Series Contains Temperature Compensation  
SOIC8  
D SUFFIX  
CASE 751  
1
8
8
1
KV11  
PECL Mode Operating Range: V = 3.0 V to 3.8 V  
CC  
ALYWG  
with V = 0 V  
EE  
TSSOP8  
DT SUFFIX  
CASE 948R  
G
1
NECL Mode Operating Range: V = 0 V  
CC  
with V = 3.0 V to 3.8 V  
EE  
Internal Input Pulldown Resistors  
Q Output will Default LOW with Inputs Open or at V  
PbFree Packages are Available  
EE  
1
4
DFN8  
MN SUFFIX  
CASE 506AA  
Q
Q
1
2
8
7
V
CC  
0
0
A
L
Y
= Assembly Location  
= Wafer Lot  
= Year  
D
D
W = Work Week  
M = Date Code  
G
Q
Q
3
4
6
5
1
1
= PbFree Package  
(Note: Microdot may be in either location)  
*For additional marking information, refer to  
Application Note AND8002/D.  
V
EE  
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 5 of this data sheet.  
Figure 1. Logic Diagram and Pinout Assignment  
© Semiconductor Components Industries, LLC, 2006  
1
Publication Order Number:  
December, 2006 Rev. 8  
MC100LVEL11/D  

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