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MC100ELT22DR2G PDF预览

MC100ELT22DR2G

更新时间: 2024-11-27 05:22:27
品牌 Logo 应用领域
安森美 - ONSEMI 转换器电平转换器驱动程序和接口锁存器接口集成电路光电二极管
页数 文件大小 规格书
8页 118K
描述
5.0 V Dual TTL to Differential PECL Translator

MC100ELT22DR2G 技术参数

是否无铅:不含铅生命周期:Active
零件包装代码:SOIC包装说明:SOP, SOP8,.25
针数:8Reach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
Factory Lead Time:1 week风险等级:5.12
Is Samacsys:N最大延迟:1.5 ns
接口集成电路类型:TTL/CMOS TO PECL TRANSLATORJESD-30 代码:R-PDSO-G8
JESD-609代码:e3长度:4.9 mm
湿度敏感等级:1位数:1
功能数量:2端子数量:8
最高工作温度:85 °C最低工作温度:-40 °C
输出特性:TOTEM-POLE输出锁存器或寄存器:NONE
输出极性:COMPLEMENTARY封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP8,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
峰值回流温度(摄氏度):260电源:5 V
认证状态:Not Qualified座面最大高度:1.75 mm
子类别:Level Translators最大供电电压:5.25 V
最小供电电压:4.75 V标称供电电压:5 V
表面贴装:YES技术:BIPOLAR
温度等级:INDUSTRIAL端子面层:Tin (Sn)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:40
宽度:3.9 mmBase Number Matches:1

MC100ELT22DR2G 数据手册

 浏览型号MC100ELT22DR2G的Datasheet PDF文件第2页浏览型号MC100ELT22DR2G的Datasheet PDF文件第3页浏览型号MC100ELT22DR2G的Datasheet PDF文件第4页浏览型号MC100ELT22DR2G的Datasheet PDF文件第5页浏览型号MC100ELT22DR2G的Datasheet PDF文件第6页浏览型号MC100ELT22DR2G的Datasheet PDF文件第7页 
MC10ELT22, MC100ELT22  
5.0 V Dual TTL to Differential  
PECL Translator  
The MC10ELT/100ELT22 is a dual TTL to differential PECL  
translator. Because PECL (Positive ECL) levels are used only +5 V  
and ground are required. The small outline 8-lead package and the low  
skew, dual gate design of the ELT22 makes it ideal for applications  
which require the translation of a clock and a data signal.  
http://onsemi.com  
MARKING  
Features  
DIAGRAMS*  
1.2 ns Typical Propagation Delay  
< 300 ps Typical Output to Output Skew  
PNP TTL Inputs for Minimal Loading  
Flow Through Pinouts  
8
1
8
8
HLT22  
KLT22  
1
ALYW  
ALYW  
SO8  
G
G
D SUFFIX  
CASE 751  
1
Operating Range: V = 4.75 V to 5.25 V with GND = 0 V  
CC  
No Internal Input Pulldown Resistors  
PbFree Packages are Available  
8
1
8
1
8
HT22  
ALYWG  
G
KT22  
ALYWG  
G
1
TSSOP8  
DT SUFFIX  
CASE 948R  
H = MC10  
K = MC100  
A = Assembly Location  
L = Wafer Lot  
Y = Year  
W = Work Week  
G
= PbFree Package  
(Note: Microdot may be in either location)  
*For additional information, see Application Note  
AND8002/D.  
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 5 of this data sheet.  
©
Semiconductor Components Industries, LLC, 2006  
1
Publication Order Number:  
November, 2006 Rev. 9  
MC10ELT22/D  

MC100ELT22DR2G 替代型号

型号 品牌 替代类型 描述 数据表
MC100ELT22DG ONSEMI

完全替代

5.0 V Dual TTL to Differential PECL Translator
MC100LVELT22DG ONSEMI

类似代替

3.3V Dual LVTTL/LVCMOS to Differential LVPECL Translator
MC100EPT22DG ONSEMI

类似代替

3.3V Dual LVTTL/LVCMOS to Differential LVPECL to Differential LVPECL

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