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MC100ELT23 PDF预览

MC100ELT23

更新时间: 2024-02-13 16:21:28
品牌 Logo 应用领域
安森美 - ONSEMI 转换器
页数 文件大小 规格书
3页 85K
描述
Dual Differential PECL to TTL Translator

MC100ELT23 数据手册

 浏览型号MC100ELT23的Datasheet PDF文件第2页浏览型号MC100ELT23的Datasheet PDF文件第3页 
SEMICONDUCTOR TECHNICAL DATA  
The MC100ELT23 is a dual differential PECL to TTL translator.  
Because PECL (Positive ECL) levels are used only +5V and ground are  
required. The small outline 8-lead SOIC package and the dual gate  
design of the ELT23 makes it ideal for applications which require the  
translation of a clock and a data signal. Because the mature MOSAIC 1.5  
process is used, low cost can be added to the list of features.  
The ELT23 is available in only the ECL 100K standard. Since there are  
no PECL outputs or an external V  
reference, the ELT23 does not  
BB  
require both ECL standard versions. The PECL inputs are differential;  
there is no specified difference between the differential input 10H and  
100K standards. Therefore, the MC100ELT23 can accept any standard  
8
differential PECL input referenced from a V  
of 5.0V.  
CC  
1
3.5ns Typical Propagation Delay  
Differential PECL Inputs  
Small Outline SOIC Package  
24mA TTL Outputs  
D SUFFIX  
PLASTIC SOIC PACKAGE  
CASE 751-05  
Flow Through Pinouts  
LOGIC DIAGRAM AND PINOUT ASSIGNMENT  
D0 1  
8
7
V
CC  
PIN DESCRIPTION  
FUNCTION  
D0  
D1  
2
3
Q0  
Q1  
PIN  
PECL  
TTL  
6
5
Qn  
Dn  
V
CC  
GND  
TTL Outputs  
Diff PECL Inputs  
+5.0V Supply  
Ground  
4
D1  
GND  
7/96  
Motorola, Inc. 1996  
REV 3  

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