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MC100ELT22DT PDF预览

MC100ELT22DT

更新时间: 2024-11-26 23:01:31
品牌 Logo 应用领域
安森美 - ONSEMI 转换器电平转换器驱动程序和接口锁存器接口集成电路光电二极管
页数 文件大小 规格书
8页 60K
描述
5VDual TTL to Differential PECL Translator

MC100ELT22DT 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:SOIC包装说明:PLASTIC, TSSOP-8
针数:8Reach Compliance Code:not_compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
Factory Lead Time:1 week风险等级:5.14
Is Samacsys:N最大延迟:1.5 ns
接口集成电路类型:TTL/CMOS TO PECL TRANSLATORJESD-30 代码:S-PDSO-G8
JESD-609代码:e0长度:3 mm
标称负供电电压:-4.5 V位数:1
功能数量:2端子数量:8
最高工作温度:85 °C最低工作温度:-40 °C
输出锁存器或寄存器:NONE输出极性:COMPLEMENTARY
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装等效代码:TSSOP8,.19封装形状:SQUARE
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH峰值回流温度(摄氏度):240
电源:-4.5 V认证状态:Not Qualified
座面最大高度:1.1 mm子类别:Level Translators
最大供电电压:5.25 V最小供电电压:4.75 V
标称供电电压:5 V表面贴装:YES
技术:ECL100K温度等级:INDUSTRIAL
端子面层:Tin/Lead (Sn90Pb10)端子形式:GULL WING
端子节距:0.65 mm端子位置:DUAL
处于峰值回流温度下的最长时间:30宽度:3 mm
Base Number Matches:1

MC100ELT22DT 数据手册

 浏览型号MC100ELT22DT的Datasheet PDF文件第2页浏览型号MC100ELT22DT的Datasheet PDF文件第3页浏览型号MC100ELT22DT的Datasheet PDF文件第4页浏览型号MC100ELT22DT的Datasheet PDF文件第5页浏览型号MC100ELT22DT的Datasheet PDF文件第6页浏览型号MC100ELT22DT的Datasheet PDF文件第7页 
MC10ELT22, MC100ELT22  
5VĄDual TTL to Differential  
PECL Translator  
The MC10ELT/100ELT22 is a dual TTL to differential PECL  
translator. Because PECL (Positive ECL) levels are used only +5 V  
and ground are required. The small outline 8-lead package and the low  
skew, dual gate design of the ELT22 makes it ideal for applications  
which require the translation of a clock and a data signal.  
http://onsemi.com  
MARKING  
1.2 ns Typical Propagation Delay  
<300 ps Typical Output to Output Skew  
PNP TTL Inputs for Minimal Loading  
Flow Through Pinouts  
DIAGRAMS*  
8
1
8
8
1
HLT22  
ALYW  
KLT22  
ALYW  
SO–8  
ESD Protection: >2 KV HBM, >200 V MM  
D SUFFIX  
CASE 751  
1
Operating Range: V = 4.75 V to 5.25 V with GND= 0 V  
CC  
No Internal Input Pulldown Resistors  
Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test  
8
8
8
HT22  
ALYW  
KT22  
ALYW  
Moisture Sensitivity Level 1  
1
TSSOP–8  
DT SUFFIX  
CASE 948R  
For Additional Information, see Application Note AND8003/D  
1
1
Flammability Rating: UL–94 code V–0 @ 1/8”,  
Oxygen Index 28 to 34  
Transistor Count = 51 devices  
L = Wafer Lot  
Y = Year  
W = Work Week  
H = MC10  
K = MC100  
A = Assembly Location  
LOGIC DIAGRAM AND PINOUT ASSIGNMENT  
Q0 1  
8
7
V
CC  
*For additional information, see Application Note  
AND8002/D  
Q0  
Q1  
2
3
D0  
D1  
ORDERING INFORMATION  
PECL  
TTL  
Device  
Package  
Shipping  
6
5
MC10ELT22D  
SO–8  
98 Units/Rail  
MC10ELT22DR2  
MC100ELT22D  
MC100ELT22DR2  
MC10ELT22DT  
SO–8  
SO–8  
2500 Tape & Reel  
98 Units/Rail  
Q1  
4
GND  
SO–8  
2500 Tape & Reel  
98 Units/Rail  
TSSOP–8  
MC10ELT22DTR2 TSSOP–8 2500 Tape & Reel  
MC100ELT22DT TSSOP–8 98 Units/Rail  
PIN DESCRIPTION  
FUNCTION  
PIN  
MC100ELT22DTR2 TSSOP–8 2500 Tape & Reel  
Qn, Qn  
Dn  
PECL Differential Outputs*  
TTL Inputs  
V
GND  
Positive Supply  
Ground  
CC  
* Output state undetermined when inputs are open.  
Semiconductor Components Industries, LLC, 2000  
1
Publication Order Number:  
October, 2000 – Rev. 4  
MC10ELT22/D  

MC100ELT22DT 替代型号

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