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MC-ACT-HDLC-NET

更新时间： 2024-01-19 10:34:35

品牌	Logo	应用领域
ACTEL		现场可编程门阵列可编程逻辑
页数	文件大小	规格书
5页	278K
描述
UTOPIA Level 3 PHY

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技术参数
数据手册

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MC-ACT-HDLC-NET 技术参数

生命周期：	Obsolete	包装说明：	,
Reach Compliance Code：	unknown	风险等级：	5.82
Is Samacsys：	N	JESD-30 代码：	R-XXMA-X
封装主体材料：	UNSPECIFIED	封装形状：	RECTANGULAR
封装形式：	MICROELECTRONIC ASSEMBLY	可编程逻辑类型：	FIELD PROGRAMMABLE GATE ARRAY
认证状态：	Not Qualified	表面贴装：	NO
端子形式：	UNSPECIFIED	端子位置：	UNSPECIFIED
Base Number Matches：	1

MC-ACT-HDLC-NET 数据手册

AvnetCore: Datasheet

Version 1.0, July 2006

UTOPIA Level 3 PHY

Intended Use:

—

ATM Cell Processors

PHY Processors

ATM Bridges & Gaskets

DSL ASSP interfaces

UNI/MAC

Microprocessor interfaces

Features:

top_slave

—

Function compatible with ATM Forum af-phy-0136.000

top_egr_slave

Asynchronous/synchronous FIFO using RAM

Up to 256 PHY ports supported

8/16/32 bit interfaces supported

Direct and polled status

TxClk

TxData

TxEnb_n

TxClav

TxSoc

rd_data

rd_enb

rd_clk

wr_data

wr_enb

a_full

fifo_16 / fifo_8

tx_utopia3_slave

rd_flag

TxPrty

TxAddr

Simple system side FIFO interface

Flow control and polling integrated

reset_n

top_ing_slave

Targeted Devices:

RxClk

RxData

RxEnb_n

RxClav

wr_data

wr_flag

wr_enb

wr_clk

rd_data

rd_enb

rd_flag

—

Axcelerator Family

fifo_16 / fifo_8

rx_utopia3_slave

RxPrty

ProASIC 3 Family

RxSoc

PLUS®

RxAddr

ProASIC

Family

Core Deliverables:

—

Netlist Version

> Compiled RTL simulation model, compliant with the Actel

Libero environment

> Netlist compatible with the Actel Designer place and route tool

—

RTL Version

> VHDL Source Code

All

Block Diagram

> User Guide

> Test Bench

UTOPIA (Universal Test and Operations PHY Interface for ATM) Level 3 defines the

interface between the ATM or LINK layer and a Physical Layer (PHY) device. The

UTOPIA Level 3 standard defines a full duplex interface with a Master/Slave format.

The Slave or LINK layer device responds to the requests from the PHY or Master

device. The Master performs PHY arbitration and initiates data transfers to and from

the Slave. The ATM forum has defined the UTOPIA Level 3 as either 8 or 32 bits in

width, at up to 104 MHz, supporting an OC48 channel at 2.5 Gbps.

Synthesis and Simulation Support:

—

Synthesis: Synplicity

Simulation: ModelSim

Other tools supported upon request

Verification:

—

Test Bench

—

Test Vectors

12 3 4 5

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