Datasheet > MBM29F080AC-55PFTR

MBM29F080AC-55PFTR

更新时间： 2024-11-22 22:06:59

品牌	Logo	应用领域
富士通 - FUJITSU		/
页数	文件大小	规格书
47页	547K
描述
8M (1M X 8) BIT

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MBM29F080AC-55PFTR 数据手册

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FUJITSU SEMICONDUCTOR

DATA SHEET

DS05-20850-2E

FLASH MEMORY

CMOS

8M (1M × 8) BIT

MBM29F080A^-55/-70/-90

■ FEATURES

•

Single 5.0 V read, write, and erase

Minimizes system level power requirements

Compatible with JEDEC-standard commands

Pinout and software compatible with single-power supply Flash

Superior inadvertent write protection

•

48-pin TSOP(I) (Package Suffix: PFTN-Normal Bend Type, PFTR-Reverse Bend Type)

40-pin TSOP(I) (Package Suffix: PTN-Normal Bend Type, PTR-Reversed Bend Type)

44-pin SOP (Package Suffix: PF)

•

Minimum 100,000 write/erase cycles

High performance

55 ns maximum access time

•

Sector erase architecture

Uniform sectors of 64 K bytes each

Any combination of sectors can be erased. Also supports full chip erase.

Embedded Erase™ Algorithms

Automatically pre-programs and erases the chip or any sector

Embedded Program™ Algorithms

•

Automatically programs and verifies data at specified address

Data Polling and Toggle Bit feature for detection of program or erase cycle completion

Ready/Busy output (RY/BY)

•

Hardware method for detection of program or erase cycle completion

Low V^CCwrite inhibit ≤ 3.2 V

Hardware RESET pin

•

Resets internal state machine to the read mode

Erase Suspend/Resume

Supports reading or programming data to a sector not being erased

Sector group protection

•

Hardware method that disables any combination of sector groups from write or erase operation (a sector group

consists of 2 adjacent sectors of 64 K bytes each)

Temporary sector groups unprotection

•

Temporary sector unprotection via the RESET pin

Embedded Erase™, Embedded Program™ and ExpressFlash™ are trademarks of Advanced Micro Devices, Inc.

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