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MB9BF468MPMC-G-JNE2 PDF预览

MB9BF468MPMC-G-JNE2

更新时间: 2024-11-07 20:37:39
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 微控制器
页数 文件大小 规格书
167页 2568K
描述
RISC Microcontroller,

MB9BF468MPMC-G-JNE2 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete包装说明:,
Reach Compliance Code:compliantHTS代码:8542.31.00.01
风险等级:5.82峰值回流温度(摄氏度):NOT SPECIFIED
处于峰值回流温度下的最长时间:NOT SPECIFIEDBase Number Matches:1

MB9BF468MPMC-G-JNE2 数据手册

 浏览型号MB9BF468MPMC-G-JNE2的Datasheet PDF文件第2页浏览型号MB9BF468MPMC-G-JNE2的Datasheet PDF文件第3页浏览型号MB9BF468MPMC-G-JNE2的Datasheet PDF文件第4页浏览型号MB9BF468MPMC-G-JNE2的Datasheet PDF文件第5页浏览型号MB9BF468MPMC-G-JNE2的Datasheet PDF文件第6页浏览型号MB9BF468MPMC-G-JNE2的Datasheet PDF文件第7页 
MB9B460R Series  
32-bit ARM® Cortex®-M4F  
FM4 Microcontroller  
The MB9B460R Series are a highly integrated 32-bit microcontrollers dedicated for embedded controllers with high-performance and  
competitive cost.  
These series are based on the ARM® Cortex®-M4F Processor with on-chip Flash memory and SRAM, and has peripheral functions  
such as Motor Control Timers, ADCs and Communication Interfaces (CAN, UART, CSIO, I2C, LIN).  
Features  
32-bit ARM® Cortex®-M4F Core  
Processor version: r0p1  
Up to 160 MHz Frequency Operation  
FPU built-in  
[SRAM]  
This is composed of three independent SRAMs (SRAM0,  
SRAM1 and SRAM2). SRAM0 is connected to I-code bus or  
D-code bus of Cortex-M4F core. SRAM1 and SRAM2 are  
connected to System bus of Cortex-M4F core.  
SRAM0: Up to 64 Kbytes  
SRAM1: Up to 32 Kbytes  
SRAM2: Up to 32 Kbytes  
Support DSP instruction  
Memory Protection Unit (MPU): improves the reliability of an  
embedded system  
External Bus Interface  
Integrated Nested Vectored Interrupt Controller (NVIC): 1  
NMI (non-maskable interrupt) and 128 peripheral interrupts  
and 16 priority levels  
Supports SRAM, NOR, NAND Flash and SDRAM device  
Up to 9 chip selects CS0 to CS8 (CS8 is only for SDRAM)  
8-/16-bit Data width  
24-bit System timer (Sys Tick): System timer for OS task  
management  
Up to 25-bit Address bit  
On-chip Memories  
Maximum Access size: 256 Mbyte  
Supports Address/Data multiplex  
Supports external RDY function  
Supports scramble function  
[Flash memory]  
These series are based on two independent on-chip Flash  
memories.  
MainFlash memory  
Up to 1024 Kbytes  
Built-in Flash Accelerator System with 16 Kbytes trace  
Possible to set the validity/invalidity of the scramble function  
for the external areas 0x6000_0000 to 0xDFFF_FFFF in 4  
Mbytes units.  
buffer memory  
The read access to Flash memory can be achieved  
without wait-cycle up to operation frequency of 72 MHz.  
Even at the operation frequency more than 72 MHz, an  
equivalent access to Flash memory can be obtained by  
Flash Accelerator System.  
Possible to set two kinds of the scramble key  
Note: It is necessary to prepare the dedicated software  
library to use the scramble function.  
Security function for code protection  
WorkFlash memory  
32 Kbytes  
Read cycle:  
CAN Interface (Max 2 channels)  
Compatible with CAN Specification 2.0A/B  
Maximum transfer rate: 1 Mbps  
Built-in 32 message buffer  
6wait-cycle: the operation frequency more than 120  
MHz, and up to 160 MHz  
4wait-cycle: the operation frequency more than 72 MHz,  
and up to 120 MHz  
2wait-cycle: the operation frequency more than 40 MHz,  
Multi-function Serial Interface (Max 8 channels)  
64 bytes with FIFO (the FIFO step numbers are variable  
depending on the settings of the communication mode or bit  
length.)  
and up to 72 MHz  
0wait-cycle: the operation frequency up to 40MHz  
Security function is shared with code protection  
Operation mode is selectable from the followings for each  
channel.  
UART  
CSIO  
LIN  
I2C  
Cypress Semiconductor Corporation  
Document Number: 002-04868 Rev.*C  
• 198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised May 16, 2017  
 
 

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